18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Functional Description The CY7C2168KV18, and CY7C2170KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the inpu

18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

封装/外壳：165-LBGA 包装：托盘 描述：IC SRAM 18MBIT PARALLEL 165FBGA 集成电路（IC） 存储器

双倍数据速率 (DDR) 同步 SRAM

封装/外壳：165-LBGA 包装：卷带（TR） 描述：IC SRAM 18MBIT PARALLEL 165FBGA 集成电路（IC） 存储器