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位置：首页 > IC中文资料第491页 > CY7C191

CY7C191价格

参考价格：￥139.2722

型号：CY7C1911KV18-250BZC 品牌：Cynergy 3 备注：这里有CY7C191多少钱，2025年最近7天走势，今日出价，今日竞价，CY7C191批发/采购报价，CY7C191行情走势销售排行榜，CY7C191报价。
型号 功能描述 生产厂家 企业 LOGO 操作
CY7C1910KV18

18-Mbit QDR짰 II SRAM Two-Word Burst Architecture

Functional Description The CY7C1312KV18, CY7C1314KV18, and CY7C1910KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911BV18

18-Mbit QDR-II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read o

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911BV18-167BZC

18-Mbit QDR-II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read o

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911BV18-200BZC

18-Mbit QDR-II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read o

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911BV18-250BZC

18-Mbit QDR-II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read o

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-167BZC

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-167BZI

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-167BZXC

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-167BZXI

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-200BZC

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-200BZI

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-200BZXC

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-200BZXI

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-250BZC

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-250BZI

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-250BZXC

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-250BZXI

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-278BZC

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-278BZI

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-278BZXC

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-278BZXI

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-300BZC

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-300BZI

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-300BZXC

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911CV18-300BZXI

18-Mbit QDR??II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911JV18

18-Mbit QDR II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911JV18-250BZC

18-Mbit QDR II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911JV18-250BZI

18-Mbit QDR II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911JV18-250BZXC

18-Mbit QDR II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911JV18-250BZXI

18-Mbit QDR II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911JV18-300BZC

18-Mbit QDR II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911JV18-300BZI

18-Mbit QDR II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911JV18-300BZXC

18-Mbit QDR II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911JV18-300BZXI

18-Mbit QDR II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911KV18

18-Mbit QDR짰 II SRAM Four-Word Burst Architecture

Functional Description The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911KV18-250BZC

18-Mbit QDR짰 II SRAM Four-Word Burst Architecture

Functional Description The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911KV18-250BZXC

18-Mbit QDR짰 II SRAM Four-Word Burst Architecture

Functional Description The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911KV18-300BZC

18-Mbit QDR짰 II SRAM Four-Word Burst Architecture

Functional Description The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911KV18-300BZXC

18-Mbit QDR짰 II SRAM Four-Word Burst Architecture

Functional Description The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1911KV18-333BZC

18-Mbit QDR짰 II SRAM Four-Word Burst Architecture

Functional Description The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916BV18

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Features • 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM u

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916BV18-167BZC

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Features • 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM u

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916BV18-200BZC

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Features • 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM u

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916BV18-250BZC

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Features • 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM u

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916CV18

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and wr

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916CV18-167BZC

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and wr

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916CV18-167BZI

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and wr

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916CV18-167BZXC

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and wr

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916CV18-167BZXI

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and wr

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916CV18-200BZC

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and wr

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916CV18-200BZI

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and wr

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916CV18-200BZXC

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and wr

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916CV18-200BZXI

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and wr

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916CV18-250BZC

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and wr

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916CV18-250BZI

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and wr

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916CV18-250BZXC

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and wr

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916CV18-250BZXI

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and wr

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916CV18-267BZC

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and wr

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1916CV18-267BZI

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and wr

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C191产品属性

  • 类型

    描述

  • 型号

    CY7C191

  • 功能描述

    静态随机存取存储器 18M QDRII 静态随机存取存储器 B4

  • RoHS

    否

  • 制造商

    Cypress Semiconductor

  • 存储容量

    16 Mbit

  • 组织

    1 M x 16

  • 访问时间

    55 ns

  • 电源电压-最大

    3.6 V

  • 电源电压-最小

    2.2 V

  • 最大工作电流

    22 uA

  • 最大工作温度

    + 85 C

  • 最小工作温度

    - 40 C

  • 安装风格

    SMD/SMT

  • 封装/箱体

    TSOP-48

  • 封装

    Tray

CY7C191供应商更多...

更新时间：2025-12-18 9:58:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
华富测量(深圳)传感技术有限公司
CY7C1911JV18-300BZC
CYPRESS
2138+
原厂标准封装
8960
代理CYPRESS全系列芯片,原装现货
询价
深圳市恒凯威科技开发有限公司
CY7C1911KV18-250BZC
Cypress(赛普拉斯)
21+
FBGA-165
30000
只做原装,质量保证
询价
深圳市威尔健半导体有限公司
CY7C1911JV18-300BZC
CYPRESS/赛普拉斯
23+
BGA
50000
全新原装正品现货,支持订货
询价
深圳市华来深电子有限公司
CY7C1911KV18-250BZC
CYPRESS
23+
BGA
8560
受权代理!全新原装现货特价热卖!
询价
深圳市正纳电子有限公司
CY7C1911KV18-250BZC
Cypress(赛普拉斯)
23+
NA
20094
正纳10年以上分销经验原装进口正品做服务做口碑有支持
询价
深圳市科芯源微电子有限公司
CY7C1911JV18-300BZC
CYPRESS/赛普拉斯
25+
BGA
119
原装正品,假一罚十!
询价
深圳诚思涵科技有限公司
CY7C1911JV18-300BZC
CYPRESS/赛普拉斯
24+
BGA272
6618
公司现货库存,支持实单
询价
深圳市河锋鑫科技有限公司
CY7C1911JV18300BZC
Cypress
22+
165FBGA (13x15)
9000
原厂渠道,现货配单
询价
贸泽芯城（深圳）电子科技有限公司
CY7C1911JV18-300BZC
CYPRESS/赛普拉斯
23+
BGA
10000
原厂授权一级代理,专业海外优势订货,价格优势、品种
询价
深圳市芯为科技有限公司
CY7C1911JV18-300BZC
Cypress
25+
电联咨询
7800
公司现货,提供拆样技术支持
询价

CY7C191芯片相关品牌

CY7C191规格书下载地址

CY7C191参数引脚图相关

CY7C191数据表相关新闻

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