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型号	功能描述	生产厂家企业	LOGO
CY7C1911CV18	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-167BZC	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-167BZI	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-167BZXC	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-167BZXI	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-200BZC	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-200BZI	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-200BZXC	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-200BZXI	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-250BZC	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-250BZI	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-250BZXC	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-250BZXI	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-278BZC	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-278BZI	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-278BZXC	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-278BZXI	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-300BZC	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-300BZI	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-300BZXC	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1911CV18-300BZXI	18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress

CY7C1911CV18供应商更多...

更新时间：2025-12-19 9:48:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市威尔健半导体有限公司	CY7C1911JV18-300BZC	CYPRESS/赛普拉斯	23+	BGA	50000	全新原装正品现货,支持订货	询价
深圳市华来深电子有限公司	CY7C1911KV18-250BZC	CYPRESS	23+	BGA	8560	受权代理!全新原装现货特价热卖!	询价
深圳市恒凯威科技开发有限公司	CY7C1911KV18-250BZC	Cypress(赛普拉斯)	21+	FBGA-165	30000	只做原装,质量保证	询价
深圳市正纳电子有限公司	CY7C1911KV18-250BZC	Cypress(赛普拉斯)	23+	NA	20094	正纳10年以上分销经验原装进口正品做服务做口碑有支持	询价
深圳市科芯源微电子有限公司	CY7C1911JV18-300BZC	CYPRESS/赛普拉斯	25+	BGA	119	原装正品,假一罚十!	询价
深圳诚思涵科技有限公司	CY7C1911JV18-300BZC	CYPRESS/赛普拉斯	24+	BGA272	6618	公司现货库存,支持实单	询价
深圳市河锋鑫科技有限公司	CY7C1911JV18300BZC	Cypress	22+	165FBGA (13x15)	9000	原厂渠道,现货配单	询价
贸泽芯城（深圳）电子科技有限公司	CY7C1911JV18-300BZC	CYPRESS/赛普拉斯	23+	BGA	10000	原厂授权一级代理,专业海外优势订货,价格优势、品种	询价
深圳市芯为科技有限公司	CY7C1911JV18-300BZC	Cypress	25+	电联咨询	7800	公司现货,提供拆样技术支持	询价
深圳市得捷芯城科技有限公司	CY7C1911JV18-300BZC	CYPRESS/赛普拉斯	24+	NA/	3369	原装现货,当天可交货,原型号开票	询价

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CY7C1911CV18芯片相关品牌

CY7C1911CV18规格书下载地址

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