Quad 2-Input OR Buffered B Series Gate . Quad 2-Input AND Buffered B Series Gate

General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also

QUAD 2-INPUT AND BUFFERED B SERIES GATE

DESCRIPTION The UTC UCD4081Bcontains four independent 2-input AND gates,they perform the function • Y=A Bin positive logic. FEATURES * 5V-10V-15V Parametric Ratings * Quad 2-Input AND Gate * Symmetrical Output Characteristics * Maximum Input Current of 1uA at 15V Over Full

CMOS High Voltage Logic

Features High Input Voltage up to 20V Symmetrical Output Characteristics Max input current 1μA at 18V over full Military Temperature Range Low Power TTL compatible Specified at 5V, 10V & 15V Direct drop-in replacement for obsolete components in long term programs.

CMOS High Voltage Logic

Features High Input Voltage up to 20V Symmetrical Output Characteristics Max input current 1μA at 18V over full Military Temperature Range Low Power TTL compatible Specified at 5V, 10V & 15V Direct drop-in replacement for obsolete components in long term programs.

Quad 2-Input OR Buffered B Series Gate . Quad 2-Input AND Buffered B Series Gate

General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also

Quad 2-Input OR Buffered B Series Gate . Quad 2-Input AND Buffered B Series Gate

General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also

QUAD 2-INPUT AND BUFFERED B SERIES GATE

DESCRIPTION The UTC UCD4081Bcontains four independent 2-input AND gates,they perform the function • Y=A Bin positive logic. FEATURES * 5V-10V-15V Parametric Ratings * Quad 2-Input AND Gate * Symmetrical Output Characteristics * Maximum Input Current of 1uA at 15V Over Full

QUAD 2-INPUT AND BUFFERED B SERIES GATE

DESCRIPTION The UTC UCD4081Bcontains four independent 2-input AND gates,they perform the function • Y=A Bin positive logic. FEATURES * 5V-10V-15V Parametric Ratings * Quad 2-Input AND Gate * Symmetrical Output Characteristics * Maximum Input Current of 1uA at 15V Over Full

CMOS AND Gate

Description CD4073BMS, CD4081BMS and CD4082BMS AND gates provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates. Features • High-Voltage Types (20V Rating) • CD4073BMS Triple 3-Input AND Gate • CD4081BMS Quad 2-I

CMOS AND Gate

Features • High-Voltage Types (20V Rating) • CD4073BMS Triple 3-Input AND Gate (No longer available or supported) • CD4081BMS Quad 2-Input AND Gate • CD4082BMS Dual 4-Input AND Gate (No longer available or supported) • Medium Speed Operation: - tPLH, tPHL = 60ns (typ) at VDD = 10V • 100 T

CMOS AND Gate

Features • High-Voltage Types (20V Rating) • CD4073BMS Triple 3-Input AND Gate (No longer available or supported) • CD4081BMS Quad 2-Input AND Gate • CD4082BMS Dual 4-Input AND Gate (No longer available or supported) • Medium Speed Operation: - tPLH, tPHL = 60ns (typ) at VDD = 10V • 100 T

CMOS AND Gate

Description CD4073BMS, CD4081BMS and CD4082BMS AND gates provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates. Features • High-Voltage Types (20V Rating) • CD4073BMS Triple 3-Input AND Gate • CD4081BMS Quad 2-I

CMOS Dual 2 Wide 2 Input AND-OR-INVERT Gate

Description CD4085BMS contains a pair of AND-OR-INVERT gates, each consisting of two 2 input AND gates driving a 3 input NOR gate. Individual inhibit controls are provided for both A-O-I gates.. The CD4085BMS is supplied in these 14 lead outline packages: Braze Seal DIP H4H Frit Seal DI

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

CMOS Dual 2 Wide 2 Input AND-OR-INVERT Gate

Description CD4085BMS contains a pair of AND-OR-INVERT gates, each consisting of two 2 input AND gates driving a 3 input NOR gate. Individual inhibit controls are provided for both A-O-I gates.. The CD4085BMS is supplied in these 14 lead outline packages: Braze Seal DIP H4H Frit Seal DI

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ™ 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ™ 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ™ 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ™ 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ™ 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ™ 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ™ 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ™ 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ™ 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ™ 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

CMOS Binary Rate Multiplier

Features • High Voltage Type (20V Rating) • Cascadable in Multiples of 4 Bits • Set to “15” Input and “15” Detect Output • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics • Maximum Input Current of 1μA at 18

CMOS Binary Rate Multiplier

Description CD4089BMS is a low power 4 bit digital rate multiplier that provides an output pulse rate that is the clock-input-pulse rate multiplied by 1/16 times the binary input. For example, when the binary input number is 13, there will be 13 output pulses for every 16 input pulses. This dev

CMOS Binary Rate Multiplier

Features: Cascadable in multiples of 4-bits Set to “15” input and “15” detect output 100% tested for gujescent current at 20 V 5.V, 10-V, and 15-V parametric ratings = Standardized, symmetrical output charactavistics = Maximum input current of 1 uA at 18 V over full package-temperatu

CMOS Binary Rate Multiplier

Features: Cascadable in multiples of 4-bits Set to “15” input and “15” detect output 100% tested for gujescent current at 20 V 5.V, 10-V, and 15-V parametric ratings = Standardized, symmetrical output charactavistics = Maximum input current of 1 uA at 18 V over full package-temperatu

CMOS Binary Rate Multiplier

Features: Cascadable in multiples of 4-bits Set to “15” input and “15” detect output 100% tested for gujescent current at 20 V 5.V, 10-V, and 15-V parametric ratings = Standardized, symmetrical output charactavistics = Maximum input current of 1 uA at 18 V over full package-temperatu

CMOS Binary Rate Multiplier

Features: Cascadable in multiples of 4-bits Set to “15” input and “15” detect output 100% tested for gujescent current at 20 V 5.V, 10-V, and 15-V parametric ratings = Standardized, symmetrical output charactavistics = Maximum input current of 1 uA at 18 V over full package-temperatu

CMOS Binary Rate Multiplier

Description CD4089BMS is a low power 4 bit digital rate multiplier that provides an output pulse rate that is the clock-input-pulse rate multiplied by 1/16 times the binary input. For example, when the binary input number is 13, there will be 13 output pulses for every 16 input pulses. This dev

CMOS Binary Rate Multiplier

Features: Cascadable in multiples of 4-bits Set to “15” input and “15” detect output 100% tested for gujescent current at 20 V 5.V, 10-V, and 15-V parametric ratings = Standardized, symmetrical output charactavistics = Maximum input current of 1 uA at 18 V over full package-temperatu

CMOS Binary Rate Multiplier

Features: Cascadable in multiples of 4-bits Set to “15” input and “15” detect output 100% tested for gujescent current at 20 V 5.V, 10-V, and 15-V parametric ratings = Standardized, symmetrical output charactavistics = Maximum input current of 1 uA at 18 V over full package-temperatu

CMOS Binary Rate Multiplier

Features: Cascadable in multiples of 4-bits Set to “15” input and “15” detect output 100% tested for gujescent current at 20 V 5.V, 10-V, and 15-V parametric ratings = Standardized, symmetrical output charactavistics = Maximum input current of 1 uA at 18 V over full package-temperatu

CMOS Binary Rate Multiplier

Features: Cascadable in multiples of 4-bits Set to “15” input and “15” detect output 100% tested for gujescent current at 20 V 5.V, 10-V, and 15-V parametric ratings = Standardized, symmetrical output charactavistics = Maximum input current of 1 uA at 18 V over full package-temperatu

电源变压器

电源变压器

电源变压器

SEMICONDUCTORS

文件：2.43533 Mbytes Page：31 Pages

CMOS High Voltage Logic

文件：517.7 Kbytes Page：4 Pages

CMOS AND GATES

文件：530.84 Kbytes Page：12 Pages

CMOS AND Gates

文件：1.42989 Mbytes Page：29 Pages

Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate

文件：101.63 Kbytes Page：7 Pages

Quad 2-Input OR, AND Buffered B Series Gate

文件：182.47 Kbytes Page：8 Pages

Quad 2-Input OR, AND Buffered B Series Gate

文件：182.47 Kbytes Page：8 Pages

Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate

文件：101.63 Kbytes Page：7 Pages

Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate

文件：101.63 Kbytes Page：7 Pages

Quad 2-Input OR, AND Buffered B Series Gate

文件：182.47 Kbytes Page：8 Pages

AND GATES

Quadruple 2-input AND Gate

Quadruple 2-input AND gate

Quadruple 2-input AND gate

B-Suffix Series CMOS Gates

B-Suffix Series CMOS Gates

B-Suffix Series CMOS Gates

B-SUFFIX SERIES CMOS GATES

B−Suffix Series CMOS Gates

B-Suffix Series CMOS Gates