丝印代码：CM085B；CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

CMOS DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATE

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Cmos Dual 2-Wide 2-Input AND-OR-INVERT Gate

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封装/外壳：14-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC 2-IN AND-OR-INV GATE 14-TSSOP 集成电路（IC） 门和反相器 - 多功能，可配置

丝印代码：CM085B；CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

Dual 2-wide 2-input AND-OR-invert gate

DESCRIPTION The HEF4085B is a dual 2-wide 2-input AND-OR-invert gate, each with an additional input (A4 or B4) which can be used as either an expander input or an inhibit input. A HIGH on A4 or B4 forces the output (OA or OB) LOW independent of the other inputs (A0 to A3 or B0 to B3). The outputs

Dual 2-wide 2-input AND-OR-invert gate

DESCRIPTION The HEF4085B is a dual 2-wide 2-input AND-OR-invert gate, each with an additional input (A4 or B4) which can be used as either an expander input or an inhibit input. A HIGH on A4 or B4 forces the output (OA or OB) LOW independent of the other inputs (A0 to A3 or B0 to B3). The outputs

Dual 2-wide 2-input AND-OR-invert gate

DESCRIPTION The HEF4085B is a dual 2-wide 2-input AND-OR-invert gate, each with an additional input (A4 or B4) which can be used as either an expander input or an inhibit input. A HIGH on A4 or B4 forces the output (OA or OB) LOW independent of the other inputs (A0 to A3 or B0 to B3). The outputs

VTP Process Photodiodes

PRODUCT DESCRIPTION Large area planar silicon mounted on a two lead ceramic substrate and coated with a layer of clear epoxy. Low junction capacitance permits fast response time.

VTP Process Photodiodes

PRODUCT DESCRIPTION Large area planar silicon mounted on a two lead ceramic substrate and coated with a layer of clear epoxy. Low junction capacitance permits fast response time.