CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC DUAL AND-ORINV GATE 14-SOIC 集成电路（IC） 门和反相器 - 多功能，可配置

CMOS DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATE

文件：527 Kbytes Page：11 Pages

Cmos Dual 2-Wide 2-Input AND-OR-INVERT Gate

文件：892.47 Kbytes Page：15 Pages

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Features: Medium-speed operation — tpyy = 90 ns; tp * 125 ns (typ.) at 10 V . Individual inhibit controls Standardized symmetrical output characteristics 100% tested for quiescent current at 20 V 8 Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at

CMOS Dual 2 Wide 2 Input AND-OR-INVERT Gate

Description CD4085BMS contains a pair of AND-OR-INVERT gates, each consisting of two 2 input AND gates driving a 3 input NOR gate. Individual inhibit controls are provided for both A-O-I gates.. The CD4085BMS is supplied in these 14 lead outline packages: Braze Seal DIP H4H Frit Seal DI

CMOS DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATE

文件：527 Kbytes Page：11 Pages

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC DUAL AND-ORINV GATE 14-SOIC 集成电路（IC） 门和反相器 - 多功能，可配置

CMOS DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATE

文件：527 Kbytes Page：11 Pages

Cmos Dual 2-Wide 2-Input AND-OR-INVERT Gate

文件：892.47 Kbytes Page：15 Pages

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