CD4023价格

参考价格:¥33.3014

型号:CD4023AE 品牌:Semiconductors 备注:这里有CD4023多少钱,2025年最近7天走势,今日出价,今日竞价,CD4023批发/采购报价,CD4023行情走势销售排行榜,CD4023报价。
型号 功能描述 生产厂家 企业 LOGO 操作
CD4023

Buffered Triple 3-Input NAND Gate

General Description These triple gates are monolithic complementary MOS(CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outp

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

CD4023

CMOS NAND Gates

Description CD4011BMS, CD4012BMS, and CD4023BMS NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. CD4011BMS - Quad 2 Input CD4012BMS - Dual 4 Input CD4023BMS - Triple 3 I

Intersil

CD4023

Buffered Triple 3-Input NAND,NOR Gate

文件:127.67 Kbytes Page:6 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

CD4023

SEMICONDUCTORS

文件:2.43533 Mbytes Page:31 Pages

etc2List of Unclassifed Manufacturers

etc未分类制造商etc2未分类制造商

CD4023

3路3输入与非门

i-coreWUXI i-CORE Electronics Co., Ltd

中微爱芯无锡中微爱芯电子有限公司

CD4023

Buffered Triple 3-Input NAND,NOR Gate

TI

德州仪器

CD4023

Buffered Triple 3-Input NAND Gate

ONSEMI

安森美半导体

CMOS NAND Gates

Features: Quiescent current specified to 15 V Maximum input leakage of 1 uA at 15 V (full package-temperature range) 1-V noise margin (full package-temperature range)

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND Gates

Description CD4011BMS, CD4012BMS, and CD4023BMS NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. CD4011BMS - Quad 2 Input CD4012BMS - Dual 4 Input CD4023BMS - Triple 3 I

Intersil

Buffered Triple 3-Input NAND Gate

General Description These triple gates are monolithic complementary MOS(CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outp

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Buffered Triple 3-Input NAND Gate

General Description These triple gates are monolithic complementary MOS(CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outp

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Buffered Triple 3-Input NAND Gate

General Description These triple gates are monolithic complementary MOS(CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outp

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Buffered Triple 3-Input NAND Gate

General Description These triple gates are monolithic complementary MOS(CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outp

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Buffered Triple 3-Input NAND Gate

General Description These triple gates are monolithic complementary MOS(CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outp

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND Gates

Features • High-Voltage Types (20V Rating) • Propagation Delay Time = 60ns (typ.) at CL = 50pF, VDD = 10V • Buffered Inputs and Outputs • Standardized Symmetrical Output Characteristics • Maximum Input Current of 1A at 18V Over Full PackageTemperature Range; 100nA at 18V and +25oC • 100 Te

RENESAS

瑞萨

CMOS NAND Gates

Description CD4011BMS, CD4012BMS, and CD4023BMS NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. CD4011BMS - Quad 2 Input CD4012BMS - Dual 4 Input CD4023BMS - Triple 3 I

Intersil

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

文件:371.28 Kbytes Page:7 Pages

TI

德州仪器

CMOS NAND Gates

文件:200.37 Kbytes Page:4 Pages

TI

德州仪器

CMOS NAND GATES

文件:371.28 Kbytes Page:7 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

Buffered Triple 3-Input NAND,NOR Gate

文件:127.67 Kbytes Page:6 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

Buffered Triple 3-Input NAND,NOR Gate

文件:127.67 Kbytes Page:6 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

Buffered Triple 3-Input NAND,NOR Gate

文件:127.67 Kbytes Page:6 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

Buffered Triple 3-Input NAND,NOR Gate

文件:127.67 Kbytes Page:6 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages

文件:523.01 Kbytes Page:12 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

封装/外壳:14-DIP(0.300",7.62mm) 包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 描述:IC GATE NAND 3CH 3-INP 14DIP 集成电路(IC) 门和反相器

TI2

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages

文件:523.01 Kbytes Page:12 Pages

TI

德州仪器

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages

文件:523.01 Kbytes Page:12 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

替换型号 功能描述 生产厂家 企业 LOGO 操作

Triple 3-input NAND Gate

HitachiHitachi Semiconductor

日立日立公司

Triple 3-input NAND gate

Philips

飞利浦

Triple 3-input NAND gate

Philips

飞利浦

B-Suffix Series CMOS Gates

ONSEMI

安森美半导体

B−Suffix Series CMOS Gates

ONSEMI

安森美半导体

B-Suffix Series CMOS Gates

Motorola

摩托罗拉

B-SUFFIX SERIES CMOS GATES

ONSEMI

安森美半导体

B-Suffix Series CMOS Gates

Motorola

摩托罗拉

B-SUFFIX SERIES CMOS GATES

ONSEMI

安森美半导体

B-Suffix Series CMOS Gates

Motorola

摩托罗拉

COMPLEMENTARY METAL OXIDE SILICON

NTE

INPUT NAND GATE

RANDE

CD4023产品属性

  • 类型

    描述

  • 型号

    CD4023

  • 制造商

    Harris Corporation

更新时间:2025-9-27 23:54:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
ROHM/罗姆
24+
SOT23-5
6000
公司现货库存,支持实单
TI(德州仪器)
24+
标准封装
7398
原厂直销,大量现货库存,交期快。价格优,支持账期
TI(德州仪器)
24+
TSSOP14
2317
只做原装,提供一站式配单服务,代工代料。BOM配单
NS
25+
SOP14
35
原装正品,假一罚十!
NS
24+
DIP14
20000
全新原厂原装,进口正品现货,正规渠道可含税!!
127
DIPTRONICS/台湾圜达
450
92
TI/德州仪器
22+
SOIC-14
500000
原装现货支持实单价优/含税
TI
24+
PDIP|14
798400
免费送样原盒原包现货一手渠道联系
FSC/ON
23+
原包装原封□□
4240
原装进口特价供应特价,原装元器件供应,支持开发样品更多详细咨询库存
FSC
25+23+
SMD
30464
绝对原装正品全新进口深圳现货

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