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CD4023价格

参考价格:¥33.3014

型号:CD4023AE 品牌:Semiconductors 备注:这里有CD4023多少钱,2026年最近7天走势,今日出价,今日竞价,CD4023批发/采购报价,CD4023行情走势销售排行榜,CD4023报价。
型号 功能描述 生产厂家 企业 LOGO 操作
CD4023

Buffered Triple 3-Input NAND Gate

General Description These triple gates are monolithic complementary MOS(CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outp

FAIRCHILD

仙童半导体

CD4023

CMOS NAND Gates

Description CD4011BMS, CD4012BMS, and CD4023BMS NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. CD4011BMS - Quad 2 Input CD4012BMS - Dual 4 Input CD4023BMS - Triple 3 I

INTERSIL

CD4023

3路3输入与非门

The CD4023 provides the positive triple 3-input NAND function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance.It operates over a recommended VDD power supply range of 3V to 15V referenced to GND (usually ground). Unused inputs must be connecte • Wide supply voltage range from 3V to 15V\n• Fully static operation\n• 5V, 10V, and 15V parametric ratings\n• Standardized symmetrical output characteristics\n• Inputs and outputs are protected against electrostatic effects\n• Specified from -40℃ to +125℃\n• Packaging information: DIP14/SOP14/TSSOP;

I-COREWUXI i-CORE Electronics Co., Ltd

中微爱芯无锡中微爱芯电子有限公司

CD4023

Buffered Triple 3-Input NAND,NOR Gate

TI

德州仪器

CD4023

Buffered Triple 3-Input NAND Gate

ONSEMI

安森美半导体

CD4023

SEMICONDUCTORS

文件:2.43533 Mbytes Page:31 Pages

ETCList of Unclassifed Manufacturers

未分类制造商

CD4023

Buffered Triple 3-Input NAND,NOR Gate

文件:127.67 Kbytes Page:6 Pages

NSC

国半

丝印代码:CD4023BE;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

丝印代码:CD4023BE;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

丝印代码:CD4023BE;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

丝印代码:CD4023BF;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

丝印代码:CD4023BF;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

丝印代码:CD4023BF3A;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

丝印代码:CD4023BF3A;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

丝印代码:CD4023BM;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

丝印代码:CD4023BM;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

丝印代码:CD4023BM;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

丝印代码:CD4023BM;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

丝印代码:CD4023B;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

丝印代码:CD4023B;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND Gates

Features: Quiescent current specified to 15 V Maximum input leakage of 1 uA at 15 V (full package-temperature range) 1-V noise margin (full package-temperature range)

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND Gates

Description CD4011BMS, CD4012BMS, and CD4023BMS NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. CD4011BMS - Quad 2 Input CD4012BMS - Dual 4 Input CD4023BMS - Triple 3 I

INTERSIL

Buffered Triple 3-Input NAND Gate

General Description These triple gates are monolithic complementary MOS(CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outp

FAIRCHILD

仙童半导体

Buffered Triple 3-Input NAND Gate

General Description These triple gates are monolithic complementary MOS(CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outp

FAIRCHILD

仙童半导体

Buffered Triple 3-Input NAND Gate

General Description These triple gates are monolithic complementary MOS(CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outp

FAIRCHILD

仙童半导体

Buffered Triple 3-Input NAND Gate

General Description These triple gates are monolithic complementary MOS(CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outp

FAIRCHILD

仙童半导体

Buffered Triple 3-Input NAND Gate

General Description These triple gates are monolithic complementary MOS(CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outp

FAIRCHILD

仙童半导体

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND Gates

Features • High-Voltage Types (20V Rating) • Propagation Delay Time = 60ns (typ.) at CL = 50pF, VDD = 10V • Buffered Inputs and Outputs • Standardized Symmetrical Output Characteristics • Maximum Input Current of 1A at 18V Over Full PackageTemperature Range; 100nA at 18V and +25oC • 100 Te

RENESAS

瑞萨

CMOS NAND Gates

Description CD4011BMS, CD4012BMS, and CD4023BMS NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. CD4011BMS - Quad 2 Input CD4012BMS - Dual 4 Input CD4023BMS - Triple 3 I

INTERSIL

丝印代码:CM023B;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

丝印代码:CM023B;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

丝印代码:CM023B;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

TI

德州仪器

CMOS NAND GATES

文件:371.28 Kbytes Page:7 Pages

TI

德州仪器

CMOS NAND Gates

文件:200.37 Kbytes Page:4 Pages

TI

德州仪器

CMOS NAND GATES

文件:371.28 Kbytes Page:7 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

Buffered Triple 3-Input NAND,NOR Gate

文件:127.67 Kbytes Page:6 Pages

NSC

国半

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

Buffered Triple 3-Input NAND,NOR Gate

文件:127.67 Kbytes Page:6 Pages

NSC

国半

Buffered Triple 3-Input NAND,NOR Gate

文件:127.67 Kbytes Page:6 Pages

NSC

国半

Buffered Triple 3-Input NAND,NOR Gate

文件:127.67 Kbytes Page:6 Pages

NSC

国半

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages

文件:523.01 Kbytes Page:12 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

封装/外壳:14-DIP(0.300",7.62mm) 包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 描述:IC GATE NAND 3CH 3-INP 14DIP 集成电路(IC) 门和反相器

TI

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages

文件:523.01 Kbytes Page:12 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages

文件:523.01 Kbytes Page:12 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.18484 Mbytes Page:19 Pages

TI

德州仪器

CMOS NAND GATES

文件:1.29026 Mbytes Page:20 Pages

TI

德州仪器

CMOS NAND GATES

文件:525.82 Kbytes Page:13 Pages

TI

德州仪器

替换型号 功能描述 生产厂家 企业 LOGO 操作

Triple 3-input NAND Gate

HITACHIHitachi Semiconductor

日立日立公司

Triple 3-input NAND gate

PHILIPS

飞利浦

Triple 3-input NAND gate

PHILIPS

飞利浦

B-Suffix Series CMOS Gates

ONSEMI

安森美半导体

B−Suffix Series CMOS Gates

ONSEMI

安森美半导体

B-Suffix Series CMOS Gates

MOTOROLA

摩托罗拉

B-SUFFIX SERIES CMOS GATES

ONSEMI

安森美半导体

B-Suffix Series CMOS Gates

MOTOROLA

摩托罗拉

B-SUFFIX SERIES CMOS GATES

ONSEMI

安森美半导体

B-Suffix Series CMOS Gates

MOTOROLA

摩托罗拉

COMPLEMENTARY METAL OXIDE SILICON

NTE

INPUT NAND GATE

RANDE

CD4023产品属性

  • 类型

    描述

  • Function:

    NAND gates

  • Description:

    Triple 3-input NAND gate

  • VCC (V):

    3.0 - 15.0

  • Logic switching levels:

    CMOS

  • Tamb (°C):

    -40~125

  • Nr of pins:

    14

  • Package:

    DIP14/SOP14/TSSOP14

更新时间:2026-5-15 14:15:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
TI
25+
N/A
7786
原装正品现货,原厂订货,可支持含税原型号开票。
TI/德州仪器
25+
SOP
32000
TI/德州仪器全新特价CD4023BM96即刻询购立享优惠#长期有货
TI
23+
14-TSSOP
15000
TI现货商!原装正品!
TI/德州仪器
25+
SOIC-14_150mil
4987
强势库存!绝对原装公司现货!
TI
24+
DIP14SOP14
130531
全新原装正品!现货库存!可开13点增值税发票
TI
25+
SOP
9500
百分百原装正品 真实公司现货库存 本公司只做原装 可
TI/德州仪器
2025+
DIP
5000
原装进口价格优 请找坤融电子!
TI
24+
DIP
15800
绝对原装现货,价格低,欢迎询购!
TI/德州仪器
2021+
SOP
9000
原装现货,随时欢迎询价
TI
23+
SOP
12560
受权代理!全新原装现货特价热卖!

CD4023数据表相关新闻