位置：首页 > IC中文资料第11710页 > 74LV10
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
74LV10 | Triple 3-input NAND gate DESCRIPTION The 74LV10 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT10. The 74LV10 provides the 3-input NAND function. FEATURES • Optimized for Low Voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typi | Philips 飞利浦 |   | |
Dual JK flip-flop with reset; negative-edge trigger DESCRIPTION The 74LV107 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT107. The 74LV107 is a dual negative-edge triggered JK-type flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs. The J and K | Philips 飞利浦 | | ||
Dual JK flip-flop with reset; negative-edge trigger DESCRIPTION The 74LV107 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT107. The 74LV107 is a dual negative-edge triggered JK-type flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs. The J and K | Philips 飞利浦 | | ||
Dual JK flip-flop with reset; negative-edge trigger DESCRIPTION The 74LV107 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT107. The 74LV107 is a dual negative-edge triggered JK-type flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs. The J and K | Philips 飞利浦 | | ||
Dual JK flip-flop with reset; negative-edge trigger DESCRIPTION The 74LV107 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT107. The 74LV107 is a dual negative-edge triggered JK-type flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs. The J and K | Philips 飞利浦 | | ||
Dual JK flip-flop with reset; negative-edge trigger DESCRIPTION The 74LV107 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT107. The 74LV107 is a dual negative-edge triggered JK-type flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs. The J and K | Philips 飞利浦 | | ||
Dual JK flip-flop with reset; negative-edge trigger DESCRIPTION The 74LV107 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT107. The 74LV107 is a dual negative-edge triggered JK-type flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs. The J and K | Philips 飞利浦 | | ||
Dual JK flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LV109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. FEATURES • Optimized for low voltage applications: 1.0 to 3.6 V • | Philips 飞利浦 | | ||
Dual JK flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LV109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. FEATURES • Optimized for low voltage applications: 1.0 to 3.6 V • | Philips 飞利浦 | | ||
Dual JK flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LV109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. FEATURES • Optimized for low voltage applications: 1.0 to 3.6 V • | Philips 飞利浦 | | ||
Dual JK flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LV109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. FEATURES • Optimized for low voltage applications: 1.0 to 3.6 V • | Philips 飞利浦 | | ||
Dual JK flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LV109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. FEATURES • Optimized for low voltage applications: 1.0 to 3.6 V • | Philips 飞利浦 | | ||
Dual JK flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LV109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. FEATURES • Optimized for low voltage applications: 1.0 to 3.6 V • | Philips 飞利浦 | | ||
Triple 3-input NAND gate DESCRIPTION The 74LV10 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT10. The 74LV10 provides the 3-input NAND function. FEATURES • Optimized for Low Voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typi | Philips 飞利浦 | | ||
Triple 3-input NAND gate DESCRIPTION The 74LV10 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT10. The 74LV10 provides the 3-input NAND function. FEATURES • Optimized for Low Voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typi | Philips 飞利浦 | | ||
Triple 3-input NAND gate DESCRIPTION The 74LV10 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT10. The 74LV10 provides the 3-input NAND function. FEATURES • Optimized for Low Voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typi | Philips 飞利浦 | | ||
Triple 3-input NAND gate DESCRIPTION The 74LV10 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT10. The 74LV10 provides the 3-input NAND function. FEATURES • Optimized for Low Voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typi | Philips 飞利浦 | | ||
Triple 3-input NAND gate DESCRIPTION The 74LV10 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT10. The 74LV10 provides the 3-input NAND function. FEATURES • Optimized for Low Voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typi | Philips 飞利浦 | |
74LV10产品属性
- 类型
描述
- 型号
74LV10
- 制造商
PHILIPS
- 制造商全称
NXP Semiconductors
- 功能描述
Triple 3-input NAND gate
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI |
2023+ |
TSSOP16 |
50000 |
原装现货 |
|||
PHI |
23+ |
NA |
20000 |
全新原装假一赔十 |
|||
恩XP |
24+ |
SOP14 |
80000 |
只做自己库存 全新原装进口正品假一赔百 可开13%增 |
|||
ti |
23+ |
NA |
2416 |
专做原装正品,假一罚百! |
|||
ph |
24+ |
N/A |
6980 |
原装现货,可开13%税票 |
|||
TI |
2018+ |
SOP |
26976 |
代理原装现货/特价热卖! |
|||
FSC |
TSSOP |
1000 |
正品原装--自家现货-实单可谈 |
||||
PHI |
25+ |
TSSOP14 |
307 |
⊙⊙新加坡大量现货库存,深圳常备现货!欢迎查询!⊙ |
|||
TI/TEXAS |
NEW |
TSSOP |
8931 |
代理全系列销售,全新原装正品,价格优势,长期供应,量大可订 |
|||
24+ |
5000 |
公司存货 |
74LV10芯片相关品牌
74LV10规格书下载地址
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74LV10数据表相关新闻
74LS26
www.jskj-ic.com
2021-9-1674LV4051PW TSSOP-16 NXP/恩智浦 模拟开关IC
原装正品现货供应 0755-28892389/13713856319；QQ:2639752116；微信：13713856319；
2021-4-2974LV4051PW TSSOP-16 NXP/恩智浦 模拟开关IC 原装正品 自家现货
原装正品现货供应 0755-28892389/13713856319；QQ:2639752116；微信：13713856319；
2021-4-2374LS386PC，74LS38PC，74LS38SC，74LS393DC，74LS393PC，74LS393SC，74LS395DC，74LS395PC，74LS40DC，74LS40PC，74LS42DC，74LS42PC，74LS447PC，74LS47PC，74LS48PC，74LS49PC，74LS502DC，74LS502PC，74LS503SC
74LS386PC，74LS38PC，74LS38SC，74LS393DC，74LS393PC，74LS393SC，74LS395DC，74LS395PC，74LS40DC，74LS40PC，74LS42DC，74LS42PC，74LS447PC，74LS47PC，74LS48PC，74LS49PC，74LS502DC，74LS502PC，74LS503SC
2019-12-1574LVC04AD百分百进口原装现货
瀚佳科技(深圳)有限公司 专业为工厂一站式BOM配单服务
2019-3-474LS90-十进制计数器;十二分频计数器;4位二进制计数器
74LS90：十进制计数器;十二分频计数器;4位二进制计数器 SN54/74LS90，SN54/74LS92和SN54/74LS93高速4位波纹型计数器，分割成两部分。每个计数器都有一个鸿沟由两节和一个分五（LS90），除以六（LS92）或 除以个（LS93）部分是由高向低过渡触发时钟输入。每一节都可以单独使用，或绑在了一起（问到CP），形成BCD，双向五元，模12模16计数器。所有 计数器有一个2输入门控主复位（清除），和LS90还有一个2输入与门控主设定（预设9）。 特点： •低功耗。通常为45兆瓦
2012-11-9
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