位置：首页 > IC中文资料第384页 > 74LS112PC
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the | MOTOROLA 摩托罗拉 |   | ||
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra | FAIRCHILD 仙童半导体 | | ||
Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) ● Quadrupie 2-Input Positive NAND Gates ● Quadruple 2-Input Positive NAND Gates (with Open Collector Output) (Continue....) | HITACHIHitachi Semiconductor 日立日立公司 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件：300.4 Kbytes Page：9 Pages | TI 德州仪器 | | ||
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra | FAIRCHILD 仙童半导体 | |
| 替换型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | MOTOROLA 摩托罗拉 | MOTOROLA | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI | | |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs | FAIRCHILD 仙童半导体 | FAIRCHILD | | |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs | FAIRCHILD 仙童半导体 | FAIRCHILD | | |
DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET, CLEAR, AND COMPLEMENTARY OUTPUTS | NSC 国半 | NSC | | |
Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI | | |
Ouadruple 2-input Positive NAND Gates | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR | TI 德州仪器 | TI | |
74LS112PC产品属性
- 类型
描述
- 型号
74LS112PC
- 制造商
Rochester Electronics LLC
- 功能描述
- Bulk
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI |
25+ |
- |
22412 |
原装正品现货,原厂订货,可支持含税原型号开票。 |
|||
TI |
25+ |
- |
18746 |
样件支持,可原厂排单订货! |
|||
MOT |
23+ |
NA |
20000 |
全新原装假一赔十 |
|||
FAIRCHILDSEMICONDUCTOR |
24+ |
NA |
80000 |
只做自己库存 全新原装进口正品假一赔百 可开13%增 |
|||
SSS |
DIP16 |
6 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
||||
TI/德州仪器 |
2026+ |
DIP |
54648 |
百分百原装现货 实单必成 欢迎询价 |
|||
TI/德州仪器 |
24+ |
DIP |
990000 |
明嘉莱只做原装正品现货 |
|||
SIGNETICS |
23+ |
DIP-16 |
9856 |
原装正品,假一罚百! |
|||
74LS112PC |
25+ |
3 |
3 |
||||
ti |
24+ |
N/A |
6980 |
原装现货,可开13%税票 |
74LS112PC规格书下载地址
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2020-9-19
DdatasheetPDF页码索引
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