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74HCT10价格

参考价格：￥0.8337

型号：74HCT107D,652 品牌：NXP 备注：这里有74HCT10多少钱，2026年最近7天走势，今日出价，今日竞价，74HCT10批发/采购报价，74HCT10行情走势销售排行榜，74HCT10报价。

型号	功能描述	生产厂家企业	LOGO
74HCT10	Triple 3-input NAND gate GENERAL DESCRIPTION The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. FEATURES • Output capability: standard • ICC categ	PHILIPS 飞利浦	PHILIPS
74HCT10	Triple 3-input NAND gate 1. General description The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Complies with JEDEC standard JESD7A • Input levels: • For74HC10	NEXPERIA 安世	NEXPERIA
74HCT107	Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J	NEXPERIA 安世	NEXPERIA
74HCT107	Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc	PHILIPS 飞利浦	PHILIPS
74HCT107D	Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc	PHILIPS 飞利浦	PHILIPS
74HCT107D	Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J	NEXPERIA 安世	NEXPERIA
74HCT107DB	Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc	PHILIPS 飞利浦	PHILIPS
74HCT107D-Q100	Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp	NEXPERIA 安世	NEXPERIA
74HCT107D-Q100	Dual JK flip-flop with reset; negative-edge trigger The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip‑flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs contr • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40°C to +85°C and from -40°C to +125°C\n\n• Input levels:• For 74HC107-Q100: CMOS level\n• For 74HCT107-Q100: TTL level\n\n• Complies with JEDEC standard no. 7A\n• ESD protection:• MIL-STD-883, method 3015 exce;	NEXPERIA 安世	NEXPERIA
74HCT107N	Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc	PHILIPS 飞利浦	PHILIPS
74HCT107PW	Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc	PHILIPS 飞利浦	PHILIPS
74HCT107-Q100	Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp	NEXPERIA 安世	NEXPERIA
74HCT109	Dual JK flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)	PHILIPS 飞利浦	PHILIPS
74HCT109	Dual JK flip-flop with set and reset; positive-edge-trigger 1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of	NEXPERIA 安世	NEXPERIA
74HCT109D	Dual JK flip-flop with set and reset; positive-edge-trigger 1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of	NEXPERIA 安世	NEXPERIA
74HCT109D	Dual JK flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)	PHILIPS 飞利浦	PHILIPS
74HCT109D	Dual JK flip-flop with set and reset; positive-edge-trigger The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock i • Input levels:• For 74HC109: CMOS level\n• For 74HCT109: TTL level\n\n• J and K inputs for easy D-type flip-flop\n• Toggle flip-flop or \"do nothing\" mode\n• Specified in compliance with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n;	NEXPERIA 安世	NEXPERIA
74HCT109DB	Dual JK flip-flop with set and reset; positive-edge-trigger The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock i • Input levels:• For 74HC109: CMOS level\n• For 74HCT109: TTL level\n\n• J and K inputs for easy D-type flip-flop\n• Toggle flip-flop or \"do nothing\" mode\n• Specified in compliance with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n;	NEXPERIA 安世	NEXPERIA
74HCT109DB	Dual JK flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)	PHILIPS 飞利浦	PHILIPS
74HCT109D-Q100	Dual JK flip-flop with set and reset; positive-edge-trigger 1. General description The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and	NEXPERIA 安世	NEXPERIA
74HCT109N	Dual JK flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)	PHILIPS 飞利浦	PHILIPS
74HCT109PW	Dual JK flip-flop with set and reset; positive-edge-trigger 1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of	NEXPERIA 安世	NEXPERIA
74HCT109PW	Dual JK flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)	PHILIPS 飞利浦	PHILIPS
74HCT109PW-Q100	Dual JK flip-flop with set and reset; positive-edge-trigger 1. General description The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and	NEXPERIA 安世	NEXPERIA
74HCT109-Q100	Dual JK flip-flop with set and reset; positive-edge-trigger 1. General description The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and	NEXPERIA 安世	NEXPERIA
74HCT10D	Triple 3-input NAND gate GENERAL DESCRIPTION The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. FEATURES • Output capability: standard • ICC categ	PHILIPS 飞利浦	PHILIPS
74HCT10D	Triple 3-input NAND gate 1. General description The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Complies with JEDEC standard JESD7A • Input levels: • For74HC10	NEXPERIA 安世	NEXPERIA
74HCT10DB	Triple 3-input NAND gate GENERAL DESCRIPTION The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. FEATURES • Output capability: standard • ICC categ	PHILIPS 飞利浦	PHILIPS
74HCT10D-Q100	Triple 3-input NAND gate 1. General description The 74HC10-Q100; 74HCT10-Q100 is a triple 3-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) stand	NEXPERIA 安世	NEXPERIA
74HCT10N	Triple 3-input NAND gate GENERAL DESCRIPTION The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. FEATURES • Output capability: standard • ICC categ	PHILIPS 飞利浦	PHILIPS
74HCT10PW	Triple 3-input NAND gate GENERAL DESCRIPTION The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. FEATURES • Output capability: standard • ICC categ	PHILIPS 飞利浦	PHILIPS
74HCT10PW	Triple 3-input NAND gate 1. General description The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Complies with JEDEC standard JESD7A • Input levels: • For74HC10	NEXPERIA 安世	NEXPERIA
74HCT10PW-Q100	Triple 3-input NAND gate 1. General description The 74HC10-Q100; 74HCT10-Q100 is a triple 3-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) stand	NEXPERIA 安世	NEXPERIA
74HCT10-Q100	Triple 3-input NAND gate 1. General description The 74HC10-Q100; 74HCT10-Q100 is a triple 3-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) stand	NEXPERIA 安世	NEXPERIA
74HCT107D,653	封装/外壳：14-SOIC（0.154"，3.90mm 宽）功能：复位包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带描述：IC FF JK TYPE DUAL 1BIT 14SO 集成电路（IC）触发器	ETC 知名厂家	ETC
74HCT107D-Q100	Dual JK flip-flop with reset; negative-edge trigger 文件：747.99 Kbytes Page：17 Pages	NEXPERIA 安世	NEXPERIA
74HCT107D-Q100J	封装/外壳：14-SOIC（0.154"，3.90mm 宽）功能：复位包装：管件描述：IC FF JK TYPE DUAL 1BIT 14SO 集成电路（IC）触发器	ETC 知名厂家	ETC
74HCT109D-Q100	Dual JK flip-flop with set and reset; positive-edge-trigger 文件：799.3 Kbytes Page：17 Pages	NEXPERIA 安世	NEXPERIA
74HCT10D.653	Triple 3-input NAND gate 文件：38.42 Kbytes Page：5 Pages	PHILIPS 飞利浦	PHILIPS
74HCT10D-Q100	Triple 3-input NAND gate 文件：697.82 Kbytes Page：13 Pages	NEXPERIA 安世	NEXPERIA
74HCT10PW-Q100	Triple 3-input NAND gate 文件：697.82 Kbytes Page：13 Pages	NEXPERIA 安世	NEXPERIA

74HCT10产品属性

类型
描述
VCC (V)：
4.5 - 5.5
Logic switching levels：
TTL
Output drive capability (mA)：
± 4
tpd (ns)：
16
fmax (MHz)：
73
Power dissipation considerations：
low
Tamb (°C)：
-40~125
Rth(j-a) (K/W)：
87
Ψth(j-top) (K/W)：
6.5
Rth(j-c) (K/W)：
45
Package name：
SO14

74HCT10供应商更多...

更新时间：2026-7-22 22:50:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
上海意淼电子科技有限公司	74HCT10N	PHIL	23+	NA	20000	全新原装假一赔十	询价
中天科工半导体（深圳）有限公司	74HCT109N	恩XP	25+	DIP	32360	NXP/恩智浦全新特价74HCT109N即刻询购立享优惠#长期有货	询价
深圳市科恒伟业电子有限公司	74HCT10DB,112	恩XP	2450+	NA	9850	只做原厂原装正品现货或订货假一赔十!	询价
深圳市正迈科技有限公司	74HCT10N652	恩XP	26+	原包装原封 □□	216000	原装进口特价供应特价，原装元器件供应，支持开发样品更多详细咨询库存	询价
深圳市欧立现代科技有限公司	74HCT107D	恩XP	26+	SOP	4800	原装现货,可开13%税票	询价
深圳市福田区绿盛电子商行	74HCT109N652	恩XP	2018+		26976	代理原装现货/特价热卖!	询价
讯运(深圳/上海)电子有限公司	74HCT10PW-Q100J	Nexperia(安世)	25+	TSSOP-14	499	全新原装	询价
深圳市中飞凌科技有限公司	74HCT109D	恩XP	26+	N/A	60000	只有原装可配单	询价
深圳市乾能惠电子有限公司	74HCT109D	恩XP	24+	N/A	20000	原厂直供原装正品	询价
深圳市华康联电子科技有限公司	74HCT109D	Nexperia	25+	N/A	20000		询价

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2020-10-16

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找IC，尽在114IC

74HCT10价格

74HCT10产品属性

74HCT10供应商更多...

74HCT10芯片相关品牌

74HCT10规格书下载地址

74HCT10参数引脚图相关

74HCT10数据表相关新闻

74HCT08PWR原现TI代理优势

74HC86D,653

74HCT123D,653是一种CMOS双单稳态多谐振荡器芯片

74HCT123PW,118是一种CMOS双单稳态多谐振荡器芯片

74HC86N 通信IC 进口原装，公司现货。

74HCT132N

DdatasheetPDF页码索引