74HCT107价格
参考价格：￥0.8337
型号：74HCT107D,652 品牌：NXP 备注：这里有74HCT107多少钱，2026年最近7天走势，今日出价，今日竞价，74HCT107批发/采购报价，74HCT107行情走势销售排行榜，74HCT107报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
74HCT107 | Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc | PHILIPS 飞利浦 |   | |
74HCT107 | Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J | NEXPERIA 安世 | | |
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J | NEXPERIA 安世 | | ||
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc | PHILIPS 飞利浦 | | ||
Dual JK flip-flop with reset; negative-edge trigger The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the sta • Complies with JEDEC standard no. 7A\n• The 74HC107: CMOS levels\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• Multiple package options\n• Specified from -40 °C to +85 °C and from -40 °C to +125 °C; | NEXPERIA 安世 | | ||
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc | PHILIPS 飞利浦 | | ||
Dual JK flip-flop with reset; negative-edge trigger The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip‑flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs contr • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40°C to +85°C and from -40°C to +125°C\n\n• Input levels:• For 74HC107-Q100: CMOS level\n• For 74HCT107-Q100: TTL level\n\n• Complies with JEDEC standard no. 7A\n• ESD protection:• MIL-STD-883, method 3015 exce; | NEXPERIA 安世 | | ||
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp | NEXPERIA 安世 | | ||
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc | PHILIPS 飞利浦 | | ||
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc | PHILIPS 飞利浦 | | ||
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp | NEXPERIA 安世 | | ||
封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF JK TYPE DUAL 1BIT 14SO 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
Dual JK flip-flop with reset; negative-edge trigger 文件：747.99 Kbytes Page：17 Pages | NEXPERIA 安世 | | ||
封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 14SO 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | |
74HCT107产品属性
- 类型
描述
- VCC (V)：
4.5 - 5.5
- Logic switching levels：
TTL
- Output drive capability (mA)：
± 4
- tpd (ns)：
16
- fmax (MHz)：
73
- Power dissipation considerations：
low
- Tamb (°C)：
-40~125
- Rth(j-a) (K/W)：
87
- Ψth(j-top) (K/W)：
6.5
- Rth(j-c) (K/W)：
45
- Package name：
SO14
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
Nexperia |
25+ |
SOIC-14 |
7734 |
样件支持,可原厂排单订货! |
|||
Nexperia(安世) |
25+ |
SOP14 |
3238 |
原装现货,免费供样,技术支持,原厂对接 |
|||
HAR |
23+ |
NA |
20000 |
全新原装假一赔十 |
|||
PHI |
24+ |
SOP14 |
20000 |
全新原厂原装，进口正品现货，正规渠道可含税！！ |
|||
PHI |
24+/25+ |
100 |
原装正品现货库存价优 |
||||
PHI |
2450+ |
SOP14 |
8850 |
只做原装正品假一赔十为客户做到零风险!! |
|||
原装PTILIPS |
SOP14 |
15620 |
一级代理 原装正品假一罚十价格优势长期供货 |
||||
Nexperia |
23+ |
TO-18 |
12800 |
原装正品代理商最优惠价格 现货或订货 |
|||
PHI |
23+ |
SOP14 |
66600 |
专业芯片配单原装正品假一罚十 |
|||
HARRIS/哈里斯 |
25+ |
IC |
880000 |
明嘉莱只做原装正品现货 |
74HCT107规格书下载地址
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