74HCT109价格
参考价格：￥0.8222
型号：74HCT109D,652 品牌：NXP 备注：这里有74HCT109多少钱，2026年最近7天走势，今日出价，今日竞价，74HCT109批发/采购报价，74HCT109行情走势销售排行榜，74HCT109报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
74HCT109 | Dual JK flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) | PHILIPS 飞利浦 |   | |
74HCT109 | Dual JK flip-flop with set and reset; positive-edge-trigger 1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of | NEXPERIA 安世 | | |
Dual JK flip-flop with set and reset; positive-edge-trigger 1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of | NEXPERIA 安世 | | ||
Dual JK flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) | PHILIPS 飞利浦 | | ||
Dual JK flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) | PHILIPS 飞利浦 | | ||
Dual JK flip-flop with set and reset; positive-edge-trigger The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock i • Input levels:• For 74HC109: CMOS level\n• For 74HCT109: TTL level\n\n• J and K inputs for easy D-type flip-flop\n• Toggle flip-flop or \"do nothing\" mode\n• Specified in compliance with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n; | NEXPERIA 安世 | | ||
Dual JK flip-flop with set and reset; positive-edge-trigger 1. General description The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and | NEXPERIA 安世 | | ||
Dual JK flip-flop with set and reset; positive-edge-trigger The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of t • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Input levels:• For 74HC109-Q100: CMOS level\n• For 74HCT109-Q100: TTL level\n\n• J and K inputs for easy D-type flip-flop\n• Toggle flip-flop or \"do nothing\" mo; | NEXPERIA 安世 | | ||
Dual JK flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) | PHILIPS 飞利浦 | | ||
Dual JK flip-flop with set and reset; positive-edge-trigger The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock i • Input levels:• For 74HC109: CMOS level\n• For 74HCT109: TTL level\n\n• J and K inputs for easy D-type flip-flop\n• Toggle flip-flop or \"do nothing\" mode\n• Specified in compliance with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n; | NEXPERIA 安世 | | ||
Dual JK flip-flop with set and reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) | PHILIPS 飞利浦 | | ||
Dual JK flip-flop with set and reset; positive-edge-trigger 1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of | NEXPERIA 安世 | | ||
Dual JK flip-flop with set and reset; positive-edge-trigger 1. General description The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and | NEXPERIA 安世 | | ||
Dual JK flip-flop with set and reset; positive-edge-trigger 1. General description The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and | NEXPERIA 安世 | | ||
封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF JK TYPE DUAL 1BIT 16SO 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
封装/外壳：16-SSOP（0.209"，5.30mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16SSOP 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
Dual JK flip-flop with set and reset; positive-edge-trigger 文件：799.3 Kbytes Page：17 Pages | NEXPERIA 安世 | |
74HCT109产品属性
- 类型
描述
- VCC (V)：
4.5 - 5.5
- Logic switching levels：
TTL
- Output drive capability (mA)：
± 4
- tpd (ns)：
17
- fmax (MHz)：
61
- Power dissipation considerations：
low
- Tamb (°C)：
-40~125
- Rth(j-a) (K/W)：
86
- Ψth(j-top) (K/W)：
6.6
- Rth(j-c) (K/W)：
44
- Package name：
SO16
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
Nexperia |
25+ |
SSOP-16-208mil |
7734 |
样件支持,可原厂排单订货! |
|||
Nexperia(安世) |
25+ |
TSSOP16 |
3238 |
原装现货,免费供样,技术支持,原厂对接 |
|||
恩XP |
2016+ |
DIP |
3605 |
只做原装,假一罚十,公司可开17%增值税发票! |
|||
HAR |
23+ |
NA |
20000 |
全新原装假一赔十 |
|||
恩XP |
25+ |
DIP |
32360 |
NXP/恩智浦全新特价74HCT109N即刻询购立享优惠#长期有货 |
|||
PHI |
2026+ |
DIP-16 |
65428 |
百分百原装现货 实单必成 |
|||
PHIL |
24+/25+ |
39 |
原装正品现货库存价优 |
||||
PHI |
23+ |
DIP |
1954 |
||||
PHI |
2450+ |
DIP |
6885 |
只做原装正品假一赔十为客户做到零风险!! |
|||
PHI |
23+ |
SMD-SO16 |
9856 |
原装正品,假一罚百! |
74HCT109规格书下载地址
74HCT109参数引脚图相关
- 8255
- 822j
- 8171
- 815ept
- 8100c
- 8051
- 8024
- 7号电池
- 7994
- 7805
- 7756
- 7705ac
- 74ls48
- 74ls373
- 74ls244
- 74ls192
- 74ls164
- 74ls138
- 74ls04
- 74ls00
- 74LCX02
- 74LCX00
- 74L71
- 74I5SN
- 74HCU04
- 74HCU
- 74HCT93
- 74HCT86
- 74HCT85
- 74HCT75
- 74HCT74
- 74HCT73
- 74HCT42
- 74HCT32
- 74HCT30
- 74HCT27
- 74HCT21
- 74HCT20
- 74HCT14
- 74HCT123D,652
- 74HCT123D
- 74HCT11PW,118
- 74HCT11PW,112
- 74HCT11N,652
- 74HCT11DB,118
- 74HCT11D,653
- 74HCT11D,652
- 74HCT112PW,112
- 74HCT112N,652
- 74HCT112D,653
- 74HCT112D,652
- 74HCT11
- 74HCT10PW,118
- 74HCT10PW,112
- 74HCT10N,652
- 74HCT10D,653
- 74HCT10D,652
- 74HCT109N,652
- 74HCT109D,653
- 74HCT109D,652
- 74HCT107N,652
- 74HCT107D,653
- 74HCT107D,652
- 74HCT10
- 74HCT08T14-13
- 74HCT08S14-13
- 74HCT08PW,118
- 74HCT08PW,112
- 74HCT08N,652
- 74HCT08DB,118
- 74HCT08D,653/BKN
- 74HCT08D,653
- 74HCT08D,652
- 74HCT08
- 74HCT04T14-13
- 74HCT04S14-13
- 74HCT04PW,118
- 74HCT04PW,112
- 74HCT04N,652
- 74HCT04N
- 74HCT04E
- 74HCT04DB,118
- 74HCT04
- 74HCT03
- 74HCT02
- 74HCT00
- 74HCT
- 74HC93N
- 74HC93D
- 74HC93
- 74HC91
- 74HC86U
- 74HC86N
- 74HC86D
- 74HC86A
- 74HC86
- 74HC85N
- 74HC85D
- 74HC85
- 74HC75N
74HCT109数据表相关新闻
74HCT08PWR原现TI代理优势
74HCT08PWR原现TI代理优势
2024-11-1474HC86D,653
74HC86D,653
2023-11-374HCT123D,653是一种CMOS双单稳态多谐振荡器芯片
74HCT123D,653芯片是一种专为专业定时和频率控制应用而设计的高性能芯片，适用于网络设备、高速通信、仪器仪表和空间应用等专业领域。
2023-6-2074HCT123PW,118是一种CMOS双单稳态多谐振荡器芯片
74HCT123PW,118是一个集成的双单稳态多谐振荡器，具有两个独立的单稳态多谐振荡器。它可以产生精确的时间延迟和脉冲宽度控制信号。
2023-6-2074HC86N 通信IC 进口原装，公司现货。
74HC86N 进口原装，公司现货。
2021-1-1974HCT132N
74HCT132N，当天发货0755-82732291全新原装现货或门市自取.
2020-10-16
DdatasheetPDF页码索引
- P1
- P2
- P3
- P4
- P5
- P6
- P7
- P8
- P9
- P10
- P11
- P12
- P13
- P14
- P15
- P16
- P17
- P18
- P19
- P20
- P21
- P22
- P23
- P24
- P25
- P26
- P27
- P28
- P29
- P30
- P31
- P32
- P33
- P34
- P35
- P36
- P37
- P38
- P39
- P40
- P41
- P42
- P43
- P44
- P45
- P46
- P47
- P48
- P49
- P50
- P51
- P52
- P53
- P54
- P55
- P56
- P57
- P58
- P59
- P60
- P61
- P62
- P63
- P64
- P65
- P66
- P67
- P68
- P69
- P70
- P71
- P72
- P73
- P74
- P75
- P76
- P77
- P78
- P79
- P80
- P81
- P82
- P83
- P84
- P85
- P86
- P87
- P88
- P89
- P90
- P91
- P92
- P93
- P94
- P95
- P96
- P97
- P98
- P99
- P100
- P101
- P102
- P103
- P104
- P105
- P106
- P107
- P108
- P109
