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位置：首页 > IC中文资料 > 74HCT109

74HCT109价格

参考价格：￥0.8222

型号：74HCT109D,652 品牌：NXP 备注：这里有74HCT109多少钱，2026年最近7天走势，今日出价，今日竞价，74HCT109批发/采购报价，74HCT109行情走势销售排行榜，74HCT109报价。
型号 功能描述 生产厂家 企业 LOGO 操作
74HCT109

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

PHILIPS

飞利浦

74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of

NEXPERIA

安世

74HCT109D

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of

NEXPERIA

安世

74HCT109D

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

PHILIPS

飞利浦

74HCT109DB

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

PHILIPS

飞利浦

74HCT109DB

Dual JK flip-flop with set and reset; positive-edge-trigger

The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock i • Input levels:• For 74HC109: CMOS level\n• For 74HCT109: TTL level\n\n• J and K inputs for easy D-type flip-flop\n• Toggle flip-flop or \"do nothing\" mode\n• Specified in compliance with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n;

NEXPERIA

安世

74HCT109D-Q100

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and

NEXPERIA

安世

74HCT109D-Q100

Dual JK flip-flop with set and reset; positive-edge-trigger

The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of t • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Input levels:• For 74HC109-Q100: CMOS level\n• For 74HCT109-Q100: TTL level\n\n• J and K inputs for easy D-type flip-flop\n• Toggle flip-flop or \"do nothing\" mo;

NEXPERIA

安世

74HCT109N

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

PHILIPS

飞利浦

74HCT109PW

Dual JK flip-flop with set and reset; positive-edge-trigger

The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock i • Input levels:• For 74HC109: CMOS level\n• For 74HCT109: TTL level\n\n• J and K inputs for easy D-type flip-flop\n• Toggle flip-flop or \"do nothing\" mode\n• Specified in compliance with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n;

NEXPERIA

安世

74HCT109PW

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

PHILIPS

飞利浦

74HCT109PW

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of

NEXPERIA

安世

74HCT109PW-Q100

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and

NEXPERIA

安世

74HCT109-Q100

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and

NEXPERIA

安世

74HCT109D,653

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF JK TYPE DUAL 1BIT 16SO 集成电路（IC） 触发器

ETC

知名厂家

74HCT109DB,112

封装/外壳：16-SSOP（0.209"，5.30mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16SSOP 集成电路（IC） 触发器

ETC

知名厂家

74HCT109D-Q100

Dual JK flip-flop with set and reset; positive-edge-trigger

文件：799.3 Kbytes Page：17 Pages

NEXPERIA

安世

74HCT109产品属性

  • 类型

    描述

  • VCC (V)：

    4.5 - 5.5

  • Logic switching levels：

    TTL

  • Output drive capability (mA)：

    ± 4

  • tpd (ns)：

    17

  • fmax (MHz)：

    61

  • Power dissipation considerations：

    low

  • Tamb (°C)：

    -40~125

  • Rth(j-a) (K/W)：

    86

  • Ψth(j-top) (K/W)：

    6.6

  • Rth(j-c) (K/W)：

    44

  • Package name：

    SO16

74HCT109供应商更多...

更新时间：2026-5-18 15:00:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
万三科技(深圳)有限公司
74HCT109D
PHI
25+
封装
500000
源自原厂成本,高价回收工厂呆滞
询价
深圳市华斯顿科技有限公司
74HCT109N
PHI
25+23+
DIP-16
8339
绝对原装正品全新进口深圳现货
询价
深圳市振宏微科技有限公司
74HCT109D
PHI
23+
SMD-SO16
9856
原装正品,假一罚百!
询价
深圳市联世界科技有限公司
74HCT109N
PHIL
24+/25+
39
原装正品现货库存价优
询价
深圳市佳鑫美电子科技有限公司
74HCT109D
PHI
25+
SOP
2987
只售原装自家现货!诚信经营!欢迎来电!
询价
深圳市莱克讯科技有限公司
74HCT109DSOP3.9
PHI
最新
SOP16-3.9MM
12600
询价
深圳市恒达亿科技有限公司
74HCT109D
恩XP
25+
SOP
3200
全新原装、诚信经营、公司现货销售
询价
深圳市拓亿芯电子有限公司
74HCT109D
PHI
25+
SOP16
30000
原装现货,假一赔十.
询价
芯有半导体（深圳）有限公司
74HCT109N
PHI
05+
PDIP
1000
自己公司全新库存绝对有货
询价
深圳市冠亿通科技有限公司
74HCT109DB,118
Nexperia USA Inc.
24+25+
16500
全新原厂原装现货!受权代理!可送样可提供技术支持!
询价

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