74HCT109价格

参考价格:¥0.8222

型号:74HCT109D,652 品牌:NXP 备注:这里有74HCT109多少钱,2025年最近7天走势,今日出价,今日竞价,74HCT109批发/采购报价,74HCT109行情走势销售排行榜,74HCT109报价。
型号 功能描述 生产厂家 企业 LOGO 操作
74HCT109

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

Philips

飞利浦

74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

Philips

飞利浦

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

Philips

飞利浦

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

Philips

飞利浦

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

Philips

飞利浦

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

封装/外壳:16-SOIC(0.154",3.90mm 宽) 功能:设置(预设)和复位 包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 描述:IC FF JK TYPE DUAL 1BIT 16SO 集成电路(IC) 触发器

ETC

知名厂家

Dual JK flip-flop with set and reset; positive-edge-trigger

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

封装/外壳:16-SSOP(0.209",5.30mm 宽) 功能:设置(预设)和复位 包装:管件 描述:IC FF JK TYPE DUAL 1BIT 16SSOP 集成电路(IC) 触发器

ETC

知名厂家

Dual JK flip-flop with set and reset; positive-edge-trigger

文件:799.3 Kbytes Page:17 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with set and reset; positive-edge-trigger

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with set and reset; positive-edge-trigger

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

74HCT109产品属性

  • 类型

    描述

  • 型号

    74HCT109

  • 制造商

    HAR

  • 功能描述

    74HCT109

更新时间:2025-9-26 13:44:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
PHI
98+
DIP-16
20
原装现货海量库存欢迎咨询
恩XP
24+
DIP14
36500
原装现货/放心购买
PHI
24+
SSOP
6540
原装现货/欢迎来电咨询
NP3
2405+
原厂封装
12500
15年芯片行业经验/只供原装正品:0755-83267371邹小姐
PHI
24+
DIP-16
9600
原装现货,优势供应,支持实单!
恩XP
2021/2022+
N/A
6000
原厂原装现货订货价格优势终端BOM表可配单提供样品
Nexperia(安世)
2021+
SSOP-16
499
PHI
23+
DIP
2964
全新原装正品现货,支持订货
恩XP
25+
SOT403
188600
全新原厂原装正品现货 欢迎咨询
PHI
05+
PDIP
1000
自己公司全新库存绝对有货

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