位置：首页 > IC中文资料 > 74HCT107PW
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
74HCT107PW | Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc | Philips 飞利浦 |   | |
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J | NEXPERIANexperia B.V. All rights reserved 安世安世半导体(中国)有限公司 | | ||
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc | Philips 飞利浦 | | ||
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J | NEXPERIANexperia B.V. All rights reserved 安世安世半导体(中国)有限公司 | | ||
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc | Philips 飞利浦 | | ||
Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc | Philips 飞利浦 | |
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
PHI |
23+ |
SOP16 |
30000 |
原装现货,假一赔十. |
|||
ph |
24+ |
N/A |
6980 |
原装现货,可开13%税票 |
|||
HAR |
23+ |
NA |
20000 |
全新原装假一赔十 |
|||
PHI |
25+ |
SOP |
2987 |
只售原装自家现货!诚信经营!欢迎来电! |
|||
恩XP |
2511 |
N/A |
6000 |
电子元器件采购降本 30%!盈慧通原厂直采,砍掉中间差价 |
|||
恩XP |
25+ |
N/A |
6000 |
原装，请咨询 |
|||
24+ |
N/A |
62000 |
一级代理-主营优势-实惠价格-不悔选择 |
||||
恩XP |
23+ |
标准封装 |
6000 |
正规渠道,只有原装! |
|||
PHI |
23+ |
SOP16 |
50000 |
全新原装正品现货,支持订货 |
|||
HAR |
24+ |
SOP |
222 |
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2020-10-16
DdatasheetPDF页码索引
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