Triple 3-input NAND gate

GENERAL DESCRIPTION The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. FEATURES • Output capability: standard • ICC categ

Triple 3-input NAND gate

1. General description The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Complies with JEDEC standard JESD7A • Input levels: • For74HC10

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of

High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS109.

High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS109.

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and

Triple 3-input NAND gate

1. General description The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Complies with JEDEC standard JESD7A • Input levels: • For74HC10

Triple 3-input NAND gate

GENERAL DESCRIPTION The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. FEATURES • Output capability: standard • ICC categ

Triple 3-input NAND gate

GENERAL DESCRIPTION The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. FEATURES • Output capability: standard • ICC categ

Triple 3-input NAND gate

1. General description The 74HC10-Q100; 74HCT10-Q100 is a triple 3-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) stand

Triple 3-input NAND gate

GENERAL DESCRIPTION The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. FEATURES • Output capability: standard • ICC categ

Triple 3-input NAND gate

GENERAL DESCRIPTION The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT10 provide the 3-input NAND function. FEATURES • Output capability: standard • ICC categ

Triple 3-input NAND gate

1. General description The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Complies with JEDEC standard JESD7A • Input levels: • For74HC10

Triple 3-input NAND gate

1. General description The 74HC10-Q100; 74HCT10-Q100 is a triple 3-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) stand

Triple 3-input NAND gate

1. General description The 74HC10-Q100; 74HCT10-Q100 is a triple 3-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) stand

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF JK TYPE DUAL 1BIT 14SO 集成电路（IC） 触发器

Dual JK flip-flop with reset; negative-edge trigger

封装/外壳：14-SSOP（0.209"，5.30mm 宽） 功能：复位 包装：卷带（TR） 描述：IC FF JK TYPE DUAL 1BIT 14SSOP 集成电路（IC） 触发器

Dual JK flip-flop with reset; negative-edge trigger

文件：747.99 Kbytes Page：17 Pages

Dual JK flip-flop with reset; negative-edge trigger

Dual JK flip-flop with reset; negative-edge trigger

Dual JK flip-flop with reset; negative-edge trigger

文件：747.99 Kbytes Page：17 Pages

Dual JK flip-flop with reset; negative-edge trigger

文件：747.99 Kbytes Page：17 Pages

High Speed CMOS Logic

文件：643.32 Kbytes Page：6 Pages

Dual JK flip-flop with set and reset; positive-edge-trigger

文件：799.3 Kbytes Page：17 Pages

Dual JK flip-flop with set and reset; positive-edge-trigger

文件：799.3 Kbytes Page：17 Pages

Triple 3-input NAND gate

文件：697.82 Kbytes Page：13 Pages

TRIPLE 3-INPUT NAND GATE

文件：125.51 Kbytes Page：4 Pages

Triple 3-input NAND gate

文件：697.82 Kbytes Page：13 Pages

Triple 3-input NAND gate

文件：697.82 Kbytes Page：13 Pages