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74HC107价格

参考价格：￥0.8528

型号：74HC107D,652 品牌：NXP 备注：这里有74HC107多少钱，2026年最近7天走势，今日出价，今日竞价，74HC107批发/采购报价，74HC107行情走势销售排行榜，74HC107报价。

型号	功能描述	生产厂家企业	LOGO
74HC107	Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc	PHILIPS 飞利浦	PHILIPS
74HC107	Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J	NEXPERIA 安世	NEXPERIA
74HC107D	Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J	NEXPERIA 安世	NEXPERIA
74HC107D	Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc	PHILIPS 飞利浦	PHILIPS
74HC107DB	Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc	PHILIPS 飞利浦	PHILIPS
74HC107DB	Dual JK flip-flop with reset; negative-edge trigger The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the sta • Complies with JEDEC standard no. 7A\n• Input levels:• The 74HC107: CMOS levels\n• The 74HCT107: TTL levels\n\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package options\n• Specified from -40 °C to +85 °C and from -40 °C to +125 °C;	NEXPERIA 安世	NEXPERIA
74HC107D-Q100	Dual JK flip-flop with reset; negative-edge trigger The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip‑flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs contr • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40°C to +85°C and from -40°C to +125°C\n\n• Input levels:• For 74HC107-Q100: CMOS level\n• For 74HCT107-Q100: TTL level\n\n• Complies with JEDEC standard no. 7A\n• ESD protection:• MIL-STD-883, method 3015 exce;	NEXPERIA 安世	NEXPERIA
74HC107D-Q100	Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp	NEXPERIA 安世	NEXPERIA
74HC107N	Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc	PHILIPS 飞利浦	PHILIPS
74HC107PW	Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc	PHILIPS 飞利浦	PHILIPS
74HC107PW	Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J	NEXPERIA 安世	NEXPERIA
74HC107PW	Dual JK flip-flop with reset; negative-edge trigger The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the sta • Complies with JEDEC standard no. 7A\n• Input levels:• The 74HC107: CMOS levels\n• The 74HCT107: TTL levels\n\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package options\n• Specified from -40 °C to +85 °C and from -40 °C to +125 °C;	NEXPERIA 安世	NEXPERIA
74HC107PW-Q100	Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp	NEXPERIA 安世	NEXPERIA
74HC107-Q100	Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp	NEXPERIA 安世	NEXPERIA
74HC107D,653	封装/外壳：14-SOIC（0.154"，3.90mm 宽）功能：复位包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带描述：IC FF JK TYPE DUAL 1BIT 14SO 集成电路（IC）触发器	ETC 知名厂家	ETC
74HC107DB,112	封装/外壳：14-SSOP（0.209"，5.30mm 宽）功能：复位包装：卷带（TR）描述：IC FF JK TYPE DUAL 1BIT 14SSOP 集成电路（IC）触发器	ETC 知名厂家	ETC
74HC107D-Q100	Dual JK flip-flop with reset; negative-edge trigger 文件：747.99 Kbytes Page：17 Pages	NEXPERIA 安世	NEXPERIA
74HC107PW-Q100	Dual JK flip-flop with reset; negative-edge trigger 文件：747.99 Kbytes Page：17 Pages	NEXPERIA 安世	NEXPERIA
74HC107-Q100	Dual JK flip-flop with reset; negative-edge trigger 文件：747.99 Kbytes Page：17 Pages	NEXPERIA 安世	NEXPERIA
CD74HC107E	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：56.86 Kbytes Page：8 Pages	TI 德州仪器	TI

74HC107产品属性

类型
描述
VCC (V)：
2.0 - 6.0
Logic switching levels：
CMOS
Output drive capability (mA)：
± 5.2
tpd (ns)：
16
fmax (MHz)：
78
Power dissipation considerations：
low
Tamb (°C)：
-40~125
Rth(j-a) (K/W)：
87
Ψth(j-top) (K/W)：
6.5
Rth(j-c) (K/W)：
45
Package name：
SO14

74HC107供应商更多...

更新时间：2026-5-18 11:11:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市纳艾斯科技有限公司	74HC107	ST	24+		80000	只做自己库存全新原装进口正品假一赔百可开13%增	询价
贸泽芯城（深圳）电子科技有限公司	74HC107A	TOSHIBA/东芝	23+	SOP-14	5000	原厂授权代理,海外优势订货渠道。可提供大量库存,详	询价
深圳市华睿芯科技有限公司	74HC107	M	24+	SOP14	20000	全新原厂原装，进口正品现货，正规渠道可含税！！	询价
深圳市坤融电子科技有限公司	74HC107D	恩XP	2025+	SOP	5000	原装进口价格优请找坤融电子!	询价
深圳市勤思达科技有限公司	74HC107	恩XP	1215+	SOP	150000	全新原装,绝对正品,公司大量现货供应.	询价
深圳市福安瓯科技有限公司	74HC107	PHI	25+	TSSOP14	2974	⊙⊙新加坡大量现货库存,深圳常备现货!欢迎查询!⊙	询价
深圳市威尔健半导体有限公司	74HC107	ST/意法	23+		50000	全新原装正品现货,支持订货	询价
深圳市华斯顿科技有限公司	74HC107	MOT	25+23+	SMD	41051	绝对原装正品全新进口深圳现货	询价
深圳市欧立现代科技有限公司	74HC107AFN	tosh	24+	N/A	6980	原装现货,可开13%税票	询价
上海意淼电子科技有限公司	74HC107	PHI	23+	SOP	20000	全新原装假一赔十	询价

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找IC，尽在114IC

74HC107价格

74HC107产品属性

74HC107供应商更多...

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74HC107规格书下载地址

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DdatasheetPDF页码索引

74HC123PW 封装TSSOP-16 单稳态多谐振荡器原装现货电子元器件