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71V3556价格
参考价格：￥24.4487
型号：71V3556S166PFG 品牌：Integrated Device Techno 备注：这里有71V3556多少钱，2026年最近7天走势，今日出价，今日竞价，71V3556批发/采购报价，71V3556行情走势销售排行榜，71V3556报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
71V3556 | 3.3V 128Kx36 ZBT Synchronous PipeLined SRAM with 3.3V I/O The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control High performance system speed 200 MHz (x18) (3.2 ns Clock-to-Data Access)\nZBTTM Feature - No dead cycles between write and read cycles\nInternally synchronized output buffer enable eliminates the need to control OE\nSingle R/W (READ/WRITE) control pin\nPositive clock-edge triggered address, data, a; | RENESAS 瑞萨 |   | |
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | | ||
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Features ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Pos | RENESAS 瑞萨 | |
71V3556产品属性
- 类型
描述
- 型号
71V3556
- 功能描述
静态随机存取存储器 128Kx36 SYNC 3.3V ZBT PIPELINED 静态随机存取存储器
- RoHS
否
- 制造商
Cypress Semiconductor
- 存储容量
16 Mbit
- 组织
1 M x 16
- 访问时间
55 ns
- 电源电压-最大
3.6 V
- 电源电压-最小
2.2 V
- 最大工作电流
22 uA
- 最大工作温度
+ 85 C
- 最小工作温度
- 40 C
- 安装风格
SMD/SMT
- 封装/箱体
TSOP-48
- 封装
Tray
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
IDT |
2026+ |
100TQFP |
65248 |
百分百原装现货 实单必成 |
|||
IDT |
1346+ |
BGA |
57 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
|||
IDT, Integrated Device Technol |
24+ |
100-TQFP(14x14) |
56200 |
一级代理/放心采购 |
|||
IDT |
23+ |
NA |
407 |
专做原装正品,假一罚百! |
|||
IDT |
2450+ |
TQFP |
9485 |
只做原装正品现货或订货假一赔十! |
|||
IDT |
25+ |
QFP |
3200 |
全新原装、诚信经营、公司现货销售 |
|||
IDT, Integrated Device Technol |
24+25+ |
16500 |
全新原厂原装现货!受权代理!可送样可提供技术支持! |
||||
71V3556S133PFG |
25+ |
950 |
950 |
||||
IDT |
2406+ |
BGA |
1850 |
诚信经营!进口原装!量大价优! |
|||
IDT |
25+ |
BGA |
8000 |
只有原装 |
71V3556芯片相关品牌
71V3556规格书下载地址
71V3556参数引脚图相关
- 7号电池
- 7994
- 7805
- 7756
- 7705ac
- 74ls48
- 74ls373
- 74ls244
- 74ls192
- 74ls164
- 74ls138
- 74ls04
- 74ls00
- 74hc595
- 74hc573
- 74hc541
- 74hc244
- 74hc164
- 7490
- 7241
- 72-007
- 72-006
- 72006
- 72-005
- 72005
- 72-004
- 72004
- 72-003
- 72003
- 72002PU
- 72002NH
- 72002E
- 72-002
- 72002
- 72001PU
- 72001NH
- 72001E
- 72-001
- 72001
- 71VR1
- 71V3578S133PFG
- 71V3577S80BGI
- 71V3577S80BGGI
- 71V3577S75PFG8
- 71V3576S150PFGI
- 71V3576S133PFGI
- 71V3576S133PFG
- 71V35761SA200BG
- 71V35761S200PFG
- 71V35761S183PFGI
- 71V35761S166PFGI
- 71V35761S166BGG
- 71V3559S85BQ
- 71V3559S80BG
- 71V3559S75PFGI
- 71V3558S133PFGI
- 71V3556SA166BGI
- 71V3556SA133BGG
- 71V3556S166PFGI
- 71V3556S166PFG
- 71V321S25TF
- 71V321L55J
- 71V321L25TFGI
- 71V321L25PFI
- 71V321L25PFGI8
- 71V321L25PFGI
- 71V321L25PFG
- 71V321L25PF
- 71V30S55TFG
- 71V30S55TF
- 71V30L35TFI
- 71V30L35TFGI
- 71V30L25TFG
- 71V256SA15YGI
- 71V256SA15YG8
- 71V256SA15YG
- 71V256SA15PZGI
- 71V256SA15PZG
- 71V256SA12YG
- 71V256SA12PZGI
- 71RIA
- 71RC80A
- 71RC70A
- 71RC60A
- 71RC50A
- 71RC30A
- 71RC20A
- 71RC10A
- 71RB60
- 71RB50
- 71RB160
- 71RB150
- 71RB140
- 71RB130
- 71RB110
- 71RB100
- 71RA80
- 71RA60
- 71RA50
- 71RA160
71V3556数据表相关新闻
716W-X2/0保证原装正品，现货价美
716W-X2/0保证原装正品，现货价美
2024-8-15721-833/001-000
721-833/001-000
2023-4-197211MD9AV2BE
7211MD9AV2BE
2022-12-287165-0796新到货只做原装，诚信为本！
16-02-0069 87439-0300 644752-5 9-1393222-1 281839-3 16-02-0115 0527451497 1379118-1 50-36-1678 189727-1 1-1102296-1 51191-0600 640250-4 171814-1009 15-24-6180 6-103672-9 345259-1 35507-0500 15-24-9144 15-24-9164 1-350944-0 794824-1 46114-1016 770586-1 502
2022-8-12719502C-2PT
https://hch01.114ic.com/
2020-11-137-215/R6C-AQ1R2B/3T原装现货
定位: Top View If - 順向電流: 20 mA 封裝: Reel 品牌: Everlight 安裝風格: SMD/SMT 濕度敏感: Yes 產品類型: LED - Standard 原廠包裝數量: 3000 子類別: LEDs
2019-11-4
DdatasheetPDF页码索引
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