位置：首页 > IC中文资料第9635页 > UR5596
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
UR5596 | MOS IC DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to pro | UTC 友顺 |   | |
UR5596 | DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to pro | UTC 友顺 | | |
UR5596 | DDR TERMINATION REGULATOR 文件：218.33 Kbytes Page：12 Pages | ETL 亚历电子 | | |
UR5596 | DDR TERMINATION REGULATOR | UTC 友顺 | | |
UR5596 | DDR TERMINATION REGULATOR 文件：219.14 Kbytes Page：12 Pages | UTC 友顺 | | |
DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to pro | UTC 友顺 | | ||
DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to pro | UTC 友顺 | | ||
DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to pro | UTC 友顺 | | ||
MOS IC DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to pro | UTC 友顺 | | ||
MOS IC DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to pro | UTC 友顺 | | ||
MOS IC DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to pro | UTC 友顺 | | ||
MOS IC DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to pro | UTC 友顺 | | ||
DDR TERMINATION REGULATOR 文件：219.14 Kbytes Page：12 Pages | UTC 友顺 | | ||
DDR TERMINATION REGULATOR 文件：223.86 Kbytes Page：12 Pages | UTC 友顺 | | ||
DDR TERMINATION REGULATOR 文件：223.86 Kbytes Page：12 Pages | UTC 友顺 | | ||
DDR TERMINATION REGULATOR 文件：219.14 Kbytes Page：12 Pages | UTC 友顺 | | ||
DDR TERMINATION REGULATOR 文件：223.86 Kbytes Page：12 Pages | UTC 友顺 | | ||
DDR TERMINATION REGULATOR 文件：219.14 Kbytes Page：12 Pages | UTC 友顺 | | ||
DDR TERMINATION REGULATOR 文件：223.86 Kbytes Page：12 Pages | UTC 友顺 | | ||
DDR TERMINATION REGULATOR 文件：223.86 Kbytes Page：12 Pages | UTC 友顺 | | ||
DDR TERMINATION REGULATOR 文件：223.86 Kbytes Page：12 Pages | UTC 友顺 | | ||
DDR TERMINATION REGULATOR 文件：219.14 Kbytes Page：12 Pages | UTC 友顺 | | ||
DDR TERMINATION REGULATOR 文件：218.33 Kbytes Page：12 Pages | ETL 亚历电子 | | ||
DDR TERMINATION REGULATOR 文件：218.33 Kbytes Page：12 Pages | ETL 亚历电子 | | ||
DDR TERMINATION REGULATOR 文件：219.14 Kbytes Page：12 Pages | UTC 友顺 | | ||
DDR TERMINATION REGULATOR 文件：223.86 Kbytes Page：12 Pages | UTC 友顺 | | ||
DDR TERMINATION REGULATOR 文件：223.86 Kbytes Page：12 Pages | UTC 友顺 | | ||
DDR TERMINATION REGULATOR 文件：218.33 Kbytes Page：12 Pages | ETL 亚历电子 | | ||
DDR TERMINATION REGULATOR 文件：218.33 Kbytes Page：12 Pages | ETL 亚历电子 | | ||
DDR TERMINATION REGULATOR 文件：223.86 Kbytes Page：12 Pages | UTC 友顺 | | ||
100 MHz to 40 GHz Linear-in-dB RMS Power Detector with 35 dB Dynamic Range FEATURES ► Ultra-wide matched input frequency range: 100 MHz to 40 GHz ► 35 dB linear dynamic range ( | AD 亚德诺 | | ||
100 MHz to 40 GHz Linear-in-dB RMS Power Detector with 35 dB Dynamic Range FEATURES ► Ultra-wide matched input frequency range: 100 MHz to 40 GHz ► 35 dB linear dynamic range ( | AD 亚德诺 | | ||
100MHz to 70GHz Linear-in-dB RMS Power Detector with 35dB Dynamic Range 文件：2.2276 Mbytes Page：22 Pages | AD 亚德诺 | | ||
100MHz to 40GHz Linear-in-dB RMS Power Detector with 35dB Dynamic Range 文件：2.3483 Mbytes Page：22 Pages | LINER 凌力尔特 | | ||
Street Fire HEI Module 文件：222 Kbytes Page：2 Pages | MALLORY | |
UR5596产品属性
- 类型
描述
- 型号
UR5596
- 制造商
UTC-IC
- 制造商全称
UTC-IC
- 功能描述
DDR TERMINATION REGULATOR
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
UTC/友顺 |
2403+ |
SOP-8 |
11809 |
原装现货!欢迎随时咨询! |
|||
UTC/友顺 |
2223+ |
SOP-8 |
26800 |
只做原装正品假一赔十为客户做到零风险 |
|||
UTC |
2016+ |
SOP8 |
4262 |
只做原装,假一罚十,公司可开17%增值税发票! |
|||
UTC/友顺 |
2023+ |
SOP-8 |
4262 |
原厂全新正品旗舰店优势现货 |
|||
UTC/友顺 |
24+ |
SOP-8 |
43200 |
郑重承诺只做原装进口现货 |
|||
25+ |
SOP |
6500 |
百分百原装正品 真实公司现货库存 本公司只做原装 可 |
||||
UTC |
23+ |
SOP8 |
5000 |
原装正品,假一罚十 |
|||
UTC |
24+ |
SOP8管装 |
6000 |
深圳原装现货价格优势 |
|||
UTC/友顺 |
2450+ |
SOP-8 |
8850 |
只做原装正品假一赔十为客户做到零风险!! |
|||
UTC/友顺 |
24+ |
SOP-8 |
9600 |
原装现货,优势供应,支持实单! |
UR5596规格书下载地址
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