DESCRIPTION

The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to provide excellent response to the load transients, and can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination.

FEATURES

* Source and sink current

* Low output voltage offset

* No external resistors required

* Linear topology

* Suspend To Ram (STR) functionality

* Low external component count

* Thermal shutdown protection