3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce)

3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce)

3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

文件：470.68 Kbytes Page：15 Pages

3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

文件：470.68 Kbytes Page：15 Pages

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC D-TYPE LATCH SGL 3-ST 20SOIC 集成电路（IC） 锁存器

3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

文件：470.68 Kbytes Page：15 Pages

3.3V Octal D-type transparent latch 3-State

DESCRIPTION The LVT573 is a high-performance BiCMOS product designed for VCC operation at 3.3V. This device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 74

3.3 V octal D-type transparent latch; 3-state

1. General description The 74LVT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change ea

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on

3.3 V octal D-type transparent latch; (3-state)

Low Voltage Octal Transparent Latch

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