3.3V Octal D-type transparent latch 3-State

DESCRIPTION The LVT573 is a high-performance BiCMOS product designed for VCC operation at 3.3V. This device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 74

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on

3.3 V octal D-type transparent latch; (3-state)

3.3 V octal D-type transparent latch; 3-state

1. General description The 74LVT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change ea

低压八路透明锁存器（带3态输出）

LVT573和LVTH573包含八个带有3态输出的闩锁，适合用于总线结构的系统应用。 当锁存使能(LE)为高电平时，锁存器对于数据而言是透明的。 当LE为低电平时，满足输入时序要求的数据被锁存。 当输出使能(OE#)为低电平时，数据显示在总线上。 当OE#为高电平时，总线输出处于高阻抗状态。 LVTH573数据输入包含总线保持功能，无需外部上拉电阻即可保持未用的输入。 这些八通道闩锁设计用于低电压(3.3V) VCC应用，也可向5V环境提供TTL接口。 LVT573和LVTH573采用先进的BiCMOS技术制造，可实现类似于5V ABT的高速运行，同时又能维持较低的CMOS功耗。 •系统在5V VCC时的输入和输出接口能力\n•总线保持数据输入无需外部上拉电阻即可保持未用的输入(74LVTH573)，另外还提供不含总线保持功能的配置(74LVT573)。\n•允许带电插/拔\n•上电/掉电高阻抗提供无干扰总线负载\n•-32 mA/+64 mA输出源电流/灌电流\n•功能上兼容74系列573\n•闩锁性能超过500 mA\n•静电放电(ESD)性能：人体模型> 2000V机械模型> 200V充电器件模型> 1000V;

Low Voltage Octal Transparent Latch

文件：342.39 Kbytes Page：13 Pages

3.3 V octal D-type transparent latch; 3-state

1. General description The 74LVT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change ea

3.3 V octal D-type transparent latch; (3-state)

3.3 V octal D-type transparent latch; (3-state)

3.3 V octal D-type transparent latch; 3-state

1. General description The 74LVT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change ea

3.3 V octal D-type transparent latch; 3-state

The 74LVT573 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an octal transparent latch coupled to eight 3-state output buffers. The two sections of the device are controlled independently by Latch Enable (LE) and Output Enable (OE) control gates. The 74LVT57 • Inputs and outputs arranged for easy interfacing to microprocessors\n• 3-state outputs for bus interfacing\n• Common output enable control\n• TTL input and output switching levels\n• Input and output interface capability to systems at 5 V supply\n• Bus hold data inputs eliminate need for external ;

3.3V Octal D-type transparent latch 3-State

DESCRIPTION The LVT573 is a high-performance BiCMOS product designed for VCC operation at 3.3V. This device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 74

3.3V Octal D-type transparent latch 3-State

DESCRIPTION The LVT573 is a high-performance BiCMOS product designed for VCC operation at 3.3V. This device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 74

3.3 V octal D-type transparent latch; (3-state)

3.3 V octal D-type transparent latch; 3-state

The 74LVT573 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an octal transparent latch coupled to eight 3-state output buffers. The two sections of the device are controlled independently by Latch Enable (LE) and Output Enable (OE) control gates. The 74LVT57 • Inputs and outputs arranged for easy interfacing to microprocessors\n• 3-state outputs for bus interfacing\n• Common output enable control\n• TTL input and output switching levels\n• Input and output interface capability to systems at 5 V supply\n• Bus hold data inputs eliminate need for external ;

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on

3.3 V octal D-type transparent latch; (3-state)

3.3V Octal D-type transparent latch 3-State

DESCRIPTION The LVT573 is a high-performance BiCMOS product designed for VCC operation at 3.3V. This device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 74

3.3 V octal D-type transparent latch; 3-state

1. General description The 74LVT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change ea

3.3V Octal D-type transparent latch 3-State

DESCRIPTION The LVT573 is a high-performance BiCMOS product designed for VCC operation at 3.3V. This device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 74

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on

3.3 V octal D-type transparent latch; 3-state

文件：323.46 Kbytes Page：17 Pages

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC OCTAL D TRANSP LATCH 20SOIC 集成电路（IC） 锁存器

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC OCTAL D TRANSP LATCH 20SOIC 集成电路（IC） 锁存器

Low Voltage Octal Transparent Latch

文件：342.39 Kbytes Page：13 Pages

Low Voltage Octal Transparent Latch

文件：342.39 Kbytes Page：13 Pages

Low Voltage Octal Transparent Latch

文件：342.39 Kbytes Page：13 Pages

Low Voltage Octal Transparent Latch

文件：342.39 Kbytes Page：13 Pages