SN74LS11价格

参考价格:¥1.9428

型号:SN74LS112AD 品牌:TI 备注:这里有SN74LS11多少钱,2025年最近7天走势,今日出价,今日竞价,SN74LS11批发/采购报价,SN74LS11行情走势销售排行榜,SN74LS11报价。
型号 功能描述 生产厂家 企业 LOGO 操作
SN74LS11

TRIPLE 3-INPUT POSITIVE-AND GATES

文件:153.88 Kbytes Page:5 Pages

TI

德州仪器

SN74LS11

TRIPLE 3-INPUT POSITIVE-AND GATES

文件:179.08 Kbytes Page:7 Pages

TI

德州仪器

SN74LS11

TRIPLE 3-INPUT POSITIVE-AND GATES

文件:1.096 Mbytes Page:17 Pages

TI

德州仪器

SN74LS11

3 通道、3 输入、4.75V 至 5.25V 双极与门

TI

德州仪器

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the

Motorola

摩托罗拉

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the

Motorola

摩托罗拉

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to cha

Motorola

摩托罗拉

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to cha

Motorola

摩托罗拉

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to cha

Motorola

摩托罗拉

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The SN54/74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed sothat when the clock goes HIGH, the inputs are enabled and data will be accepted.The logic level of the J and K inputs may be allowed to change when the

Motorola

摩托罗拉

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The SN54/74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed sothat when the clock goes HIGH, the inputs are enabled and data will be accepted.The logic level of the J and K inputs may be allowed to change when the

Motorola

摩托罗拉

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE LOW POWER SCHOTTKY

Motorola

摩托罗拉

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE LOW POWER SCHOTTKY

Motorola

摩托罗拉

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

文件:300.4 Kbytes Page:9 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

文件:300.4 Kbytes Page:9 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR

文件:697.41 Kbytes Page:17 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS

文件:1.32368 Mbytes Page:20 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR

文件:697.41 Kbytes Page:17 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS

文件:1.32368 Mbytes Page:20 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

文件:300.4 Kbytes Page:9 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR

文件:697.41 Kbytes Page:17 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS

文件:1.32368 Mbytes Page:20 Pages

TI

德州仪器

封装/外壳:16-SOIC(0.154",3.90mm 宽) 功能:设置(预设)和复位 包装:卷带(TR) 描述:IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路(IC) 触发器

TI2

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR

文件:697.41 Kbytes Page:17 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR

文件:697.41 Kbytes Page:17 Pages

TI

德州仪器

封装/外壳:16-SOIC(0.154",3.90mm 宽) 功能:设置(预设)和复位 包装:卷带(TR) 描述:IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路(IC) 触发器

TI2

德州仪器

DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS

文件:1.32368 Mbytes Page:20 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS

文件:1.32368 Mbytes Page:20 Pages

TI

德州仪器

74系列逻辑芯片

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR

文件:697.41 Kbytes Page:17 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

文件:300.4 Kbytes Page:9 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR

文件:697.41 Kbytes Page:17 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS

文件:1.32368 Mbytes Page:20 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR

文件:697.41 Kbytes Page:17 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS

文件:1.32368 Mbytes Page:20 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR

文件:697.41 Kbytes Page:17 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR

文件:697.41 Kbytes Page:17 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

文件:300.4 Kbytes Page:9 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

文件:300.4 Kbytes Page:9 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET

文件:259.97 Kbytes Page:6 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET

文件:259.97 Kbytes Page:6 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET

文件:259.97 Kbytes Page:6 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK

文件:240.11 Kbytes Page:8 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK

文件:240.11 Kbytes Page:8 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK

文件:240.11 Kbytes Page:8 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK

文件:240.11 Kbytes Page:8 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK

文件:240.11 Kbytes Page:8 Pages

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK

文件:240.11 Kbytes Page:8 Pages

TI

德州仪器

TRIPLE 3-INPUT POSITIVE-AND GATES

文件:179.08 Kbytes Page:7 Pages

TI

德州仪器

TRIPLE 3-INPUT POSITIVE-AND GATES

文件:153.88 Kbytes Page:5 Pages

TI

德州仪器

TRIPLE 3-INPUT POSITIVE-AND GATES

文件:1.096 Mbytes Page:17 Pages

TI

德州仪器

TRIPLE 3-INPUT POSITIVE-AND GATES

文件:1.096 Mbytes Page:17 Pages

TI

德州仪器

TRIPLE 3-INPUT POSITIVE-AND GATES

文件:1.096 Mbytes Page:17 Pages

TI

德州仪器

TRIPLE 3-INPUT POSITIVE-AND GATES

文件:179.08 Kbytes Page:7 Pages

TI

德州仪器

TRIPLE 3-INPUT POSITIVE-AND GATES

文件:1.096 Mbytes Page:17 Pages

TI

德州仪器

TRIPLE 3-INPUT POSITIVE-AND GATES

文件:1.096 Mbytes Page:17 Pages

TI

德州仪器

TRIPLE 3-INPUT POSITIVE-AND GATES

文件:179.08 Kbytes Page:7 Pages

TI

德州仪器

TRIPLE 3-INPUT POSITIVE-AND GATES

文件:153.88 Kbytes Page:5 Pages

TI

德州仪器

TRIPLE 3-INPUT POSITIVE-AND GATES

文件:179.08 Kbytes Page:7 Pages

TI

德州仪器

替换型号 功能描述 生产厂家 企业 LOGO 操作

Triple 3-Input AND Gate

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

TRIPLE 3-INPUT AND GATE

ETC1List of Unclassifed Manufacturers

etc未分类制造商未分类制造商

TRIPLE 3-INPUT AND GATE

ETC1List of Unclassifed Manufacturers

etc未分类制造商未分类制造商

TRIPLE 3-INPUT AND GATE

ETC1List of Unclassifed Manufacturers

etc未分类制造商未分类制造商

Triple 3-Input AND Gates

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

Triple 3-Input AND Gate

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Triple 3-input Positive AND Gates(with Open Collector Outputs)

HitachiHitachi Semiconductor

日立日立公司

Triple 3-input Positive AND Gates (with Open Collector Outputs)

RENESAS

瑞萨

Ouadruple 2-input Positive NAND Gates

HitachiHitachi Semiconductor

日立日立公司

Triple 3-input Positive AND Gates (with Open Collector Outputs)

RENESAS

瑞萨

SN74LS11产品属性

  • 类型

    描述

  • 型号

    SN74LS11

  • 功能描述

    触发器 Dual Neg-Edge-Trig J-K Flip-Flop

  • RoHS

  • 制造商

    Texas Instruments

  • 电路数量

    2

  • 逻辑系列

    SN74

  • 逻辑类型

    D-Type Flip-Flop

  • 极性

    Inverting, Non-Inverting

  • 输入类型

    CMOS

  • 传播延迟时间

    4.4 ns

  • 高电平输出电流

    - 16 mA

  • 低电平输出电流

    16 mA

  • 电源电压-最大

    5.5 V

  • 最大工作温度

    + 85 C

  • 安装风格

    SMD/SMT

  • 封装/箱体

    X2SON-8

  • 封装

    Reel

更新时间:2025-9-27 22:59:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
TI(德州仪器)
24+
SOP14
942
只做原装,提供一站式配单服务,代工代料。BOM配单
TI/德州仪器
24+
NA/
3519
原厂直销,现货供应,账期支持!
TI
23+
SOP
20000
全新原装假一赔十
TI
24+
DIP
30000
原装正品公司现货,假一赔十!
TI
三年内
1983
只做原装正品
TI/德州仪器
25+
原厂封装
10280
原厂授权代理,专注军工、汽车、医疗、工业、新能源!
TI(德州仪器)
2024+
PDIP-14
500000
诚信服务,绝对原装原盘
TI/德州仪器
25+
SOP
880000
明嘉莱只做原装正品现货
TI
23+
DIP
65480
TI
DIP
25635
一级代理 原装正品假一罚十价格优势长期供货

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