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SN74F112DR价格
参考价格：￥1.5790
型号：SN74F112DR 品牌：TI 备注：这里有SN74F112DR多少钱，2025年最近7天走势，今日出价，今日竞价，SN74F112DR批发/采购报价，SN74F112DR行情走势销售排行榜，SN74F112DR报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
SN74F112DR | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of t | TI 德州仪器 |   | |
SN74F112DR | 封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路（IC） 触发器 | TI 德州仪器 | | |
SN74F112DR | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP 文件：627.07 Kbytes Page：13 Pages | TI 德州仪器 | | |
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of t | TI 德州仪器 | | ||
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP 文件：627.07 Kbytes Page：13 Pages | TI 德州仪器 | | ||
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP 文件：627.07 Kbytes Page：13 Pages | TI 德州仪器 | | ||
Dual J-K negative edge-triggered flip-flop DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level | Philips 飞利浦 | | ||
Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J | Fairchild 仙童半导体 | | ||
Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J | Fairchild 仙童半导体 | | ||
Dual JK Negative Edge-Triggered Flip-Flop 文件：83.34 Kbytes Page：7 Pages | Fairchild 仙童半导体 | | ||
Dual JK Negative Edge-Triggered Flip-Flop 文件：83.34 Kbytes Page：7 Pages | Fairchild 仙童半导体 | |
SN74F112DR产品属性
- 类型
描述
- 型号
SN74F112DR
- 功能描述
触发器 Dual J K NEG Edge Triggered FlipFlop
- RoHS
否
- 制造商
Texas Instruments
- 电路数量
2
- 逻辑系列
SN74
- 逻辑类型
D-Type Flip-Flop
- 极性
Inverting, Non-Inverting
- 输入类型
CMOS
- 传播延迟时间
4.4 ns
- 高电平输出电流
- 16 mA
- 低电平输出电流
16 mA
- 电源电压-最大
5.5 V
- 最大工作温度
+ 85 C
- 安装风格
SMD/SMT
- 封装/箱体
X2SON-8
- 封装
Reel
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI |
25+ |
SOIC16 |
4500 |
全新原装、诚信经营、公司现货销售! |
|||
TMS |
06+ |
SOIC |
1000 |
自己公司全新库存绝对有货 |
|||
TI |
23+ |
SOP16 |
5000 |
全新原装,支持实单,非诚勿扰 |
|||
Texas Instruments |
23+ |
16-SOIC |
4500 |
特惠实单价格秒出原装正品假一罚万 |
|||
SN74F112DR |
25+ |
1292 |
1292 |
||||
TI(德州仪器) |
2021+ |
SOIC-16 |
499 |
||||
TI |
24+ |
6000 |
原装现货,特价销售 |
||||
TI/德州仪器 |
24+ |
SOP16 |
33487 |
郑重承诺只做原装进口现货 |
|||
TI |
23+ |
NA |
20000 |
||||
TI |
22+ |
16SOIC |
9000 |
原厂渠道,现货配单 |
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