位置：首页 > IC中文资料第3027页 > N74F113
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
Dual J-K negative edge-triggered flip-flops without reset DESCRIPTION The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level | Philips 飞利浦 |   | ||
Dual J-K negative edge-triggered flip-flops without reset DESCRIPTION The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level | Philips 飞利浦 | | ||
Dual J-K negative edge-triggered flip-flops without reset | ETC 知名厂家 | ETC | | |
Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as lo | Fairchild 仙童半导体 | | ||
Dual J-K negative edge-triggered flip-flops without reset DESCRIPTION The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level | Philips 飞利浦 | | ||
Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as lo | Fairchild 仙童半导体 | | ||
Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as lo | Fairchild 仙童半导体 | | ||
Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as lo | Fairchild 仙童半导体 | |
N74F113产品属性
- 类型
描述
- 型号
N74F113
- 制造商
Freescale Semiconductor
- 功能描述
Flip Flop, Dual, J/K Type, 14 Pin, Plastic, SOP
- 制造商
North American Philips Discrete Products Div
- 功能描述
Flip Flop, Dual, J/K Type, 14 Pin, Plastic, SOP
- 制造商
NXP Semiconductors
- 功能描述
Flip Flop, Dual, J/K Type, 14 Pin, Plastic, SOP
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
PHI |
21+ |
SOP |
10000 |
原装现货假一罚十 |
|||
NEXPERIA/安世 |
19+ |
NA |
5000 |
原装进口香港现货 |
|||
PHI |
23+ |
SOP |
89630 |
当天发货全新原装现货 |
|||
PHI |
24+ |
NA |
990000 |
明嘉莱只做原装正品现货 |
|||
恩XP |
2023+ |
3.9MM |
8800 |
正品渠道现货 终端可提供BOM表配单。 |
|||
恩XP |
24+ |
原厂封装 |
5700 |
原装现货假一罚十 |
|||
恩XP |
23+ |
SOP14 |
8650 |
受权代理!全新原装现货特价热卖! |
|||
PHI |
24+ |
NA/ |
4450 |
原装现货,当天可交货,原型号开票 |
|||
恩XP |
08+ |
3.9MM |
2500 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
|||
PHIL |
24+/25+ |
2785 |
原装正品现货库存价优 |
N74F113规格书下载地址
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2019-12-13
DdatasheetPDF页码索引
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