LOW-VOLTAGE 1:9 DIFFERENTIAL ECL/PECL CLOCK DRIVER

The MC100LVE111 is a low skew 1−to−9 differential driver, designed with clock distribution in mind. The MC100LVE111’s function and performance are similar to the popular MC100E111, with the added feature of low voltage operation. It accepts one signal input, which can be either differential or sin

LOW-VOLTAGE 1:9 DIFFERENTIAL ECL/PECL CLOCK DRIVER

The MC100LVE111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The MC100LVE111’s function and performance are similar to the popular MC100E111, with the added feature of low voltage operation. It accepts one signal input, which can be either differential or sin

LOW-VOLTAGE 1:9 DIFFERENTIAL ECL/PECL CLOCK DRIVER

The MC100LVE111 is a low skew 1−to−9 differential driver, designed with clock distribution in mind. The MC100LVE111’s function and performance are similar to the popular MC100E111, with the added feature of low voltage operation. It accepts one signal input, which can be either differential or sin

LOW-VOLTAGE 1:9 DIFFERENTIAL ECL/PECL CLOCK DRIVER

The MC100LVE111 is a low skew 1−to−9 differential driver, designed with clock distribution in mind. The MC100LVE111’s function and performance are similar to the popular MC100E111, with the added feature of low voltage operation. It accepts one signal input, which can be either differential or sin

LOW VOLTAGE 16:1 MULTIPLEXER

The MC100LVE164 is a 16:1 multiplexer with a differential output. The select inputs (SEL0, 1, 2, 3 ) control which one of the sixteen data inputs (A0 − A15) is propragated to the output. The device is functionally equivalent to the MC100E164 except it operates from a 3.3 V supply. The device is pa

Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer

Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer ECL/PECL Compatible The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features f

Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer

Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer ECL/PECL Compatible The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features f

Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer

Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer ECL/PECL Compatible The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features f

Low Voltage 1:15 Differential 첨1첨2 ECL/PECL Clock Driver

3.3 V/5.0 VECL 1:15 Differential ÷1/÷2 Clock Driver The MC100LVE222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be differential or used single−ended (with VBB output reference bypassed and connected to t

Low Voltage 1:15 Differential 첨1첨2 ECL/PECL Clock Driver

3.3 V/5.0 VECL 1:15 Differential ÷1/÷2 Clock Driver The MC100LVE222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be differential or used single−ended (with VBB output reference bypassed and connected to t

Low Voltage 1:15 Differential 첨1첨2 ECL/PECL Clock Driver

3.3 V/5.0 VECL 1:15 Differential ÷1/÷2 Clock Driver The MC100LVE222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be differential or used single−ended (with VBB output reference bypassed and connected to t

LOW VOLTAGE 2:8 DIFFERENTIAL FANOUT BUFFER

Description The MC100LVE310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The LVE310 offers two selectable clock inputs to allow for redundant or t

4-Input OR/NOR

Description The MC100LVEL01 is a 4−input OR/NOR gate. The device is functionally equivalent to the EL01 device and works from a 3.3 V supply. With AC performance similar to the EL01 device, the LVEL01 is ideal for low voltage applications which require the ultimate in AC performance. Features •

2-Input Differential AND/NAND

Description The MC100LVEL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the MC100EL05 device and operates from a 3.3 V supply voltage. With propagation delays and output transition times equivalent to the EL05, the LVEL05 is ideally suited for those applicati

Low Voltage 1:2 Differential Fanout Buffer

Description The MC100LVEL11 is a differential 1:2 fanout buffer. The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times significantly improved over the E111, the LVEL11 is ideally suited for those appl

Low Impedance Driver

Description The MC100LVEL12 is a low impedance drive buffer. With two pairs of OR/NOR outputs the device is ideally suited for high drive applications such as memory addressing. The device is functionally equivalent to the EL12 device and operates from a 3.3 V power supply. With propagation delay

Dual 1:3 Fanout Buffer

Description The MC100LVEL13 is a dual, fully differential 1:3 fanout buffer. The Low Output−Output Skew of the device makes it ideal for distributing two different frequency synchronous signals. Features • 500 ps Typical Propagation Delays • 50 ps Output−Output Skews • ESD Protection: >2 kV H

1:5 Clock Distribution Chip

Description The MC100LVEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and

1:5 Clock Distribution Chip

Description The MC100LVEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and

14-Bit, 80 MSPS/105 MSPS A/D Converter

GENERAL DESCRIPTION The AD6645 is a high speed, high performance, monolithic 14-bit analog-to-digital converter (ADC). All necessary functions, including track-and-hold (T/H) and reference, are included on the chip to provide a complete conversion solution. The AD6645 provides CMOS-compatible dig

Differential Receiver

Description The MC100LVEL16 is a differential receiver. The device is functionally equivalent to the EL16 device, operating from a 3.3 V supply. The LVEL16 exhibits a wider VIHCMR range than its EL16 counterpart. With output transition times and propagation delays comparable to the EL16 the LVEL1

Low-Voltage Quad Differential Receiver

Description The MC100LVEL17 is a 3.3 V ECL, quad differential receiver. The device is functionally equivalent to the E116 device with the capability of operation from either a −3.3 V or +3.3 V supply voltage. Features • 325 ps Propagation Delay • High Bandwidth Output Transitions • The 100 Se

Dual Differential Data and Clock D Flip-Flop With Set and Reset

Description The MC100LVEL29 is a dual master−slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. The MC100LVEL29 is pin and functionally equivalent to the MC100EL29. Data enters the master latch when the clock is LOW and transfers to the slave upon a

Triple D Flip-Flop With Set and Reset

Description The MC100LVEL30 is a triple master−slave D flip−flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the clock input. In addition to a common Set input individual Reset inputs are provided fo

D Flip-Flop With Set and Reset

Description The MC100LVEL31 is a D flip-flop with set and reset. The device is functionally equivalent to the EL31 device but operates from a 3.3 V supply. With propagation delays and output transition times essentially equivalent to the EL31, the LVEL31 is ideally suited for those applications w

첨2 Divider

Description The MC100LVEL32 is an integrated ÷2 divider. The LVEL32 is functionally identical to the EL32, but operates from a 3.3 V supply. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random state; the reset allows for the

첨2 Divider

Description The MC100LVEL32 is an integrated ÷2 divider. The LVEL32 is functionally identical to the EL32, but operates from a 3.3 V supply. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random state; the reset allows for the

첨2 Divider

Description The MC100LVEL32 is an integrated ÷2 divider. The LVEL32 is functionally identical to the EL32, but operates from a 3.3 V supply. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random state; the reset allows for the

3.3V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltag

3.3V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltag

3.3V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltag

3.3V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltag

3.3V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltag

3.3V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltag

3.3V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltag

3.3V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltag

3.3V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC100LVEL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltag

1:4 첨1/첨2 ECL/PECL Clock Fanout Buffer

Description The MC100LVEL37 is a fully differential 1:4 fanout buffer. The device offers two outputs at ÷1 of the input frequency, and two outputs at ÷2 of the input frequency. The Low Output−Output Skew of the device makes it ideal for distributing 1x and 1/2x frequency synchronous signals. Fea

첨2, 첨4/6 Clock Generation Chip

Description The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differen

3.3V ECL 첨2/4, 첨4/6 Clock Generation Chip

Description The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differ

첨2/4,첨4/6 Clock Generation Chip

The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The MC100EL39 is pin and functionally equivalent to the MC100LVEL39 but is specified for operation at the standard 100K ECL voltage supply. • 50ps Output-to-Output S

첨2/4,첨4/6 Clock Generation Chip

The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The MC100EL39 is pin and functionally equivalent to the MC100LVEL39 but is specified for operation at the standard 100K ECL voltage supply. • 50ps Output-to-Output S

3.3V ECL 첨2/4, 첨4/6 Clock Generation Chip

Description The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differ

3.3V ECL 첨2/4, 첨4/6 Clock Generation Chip

Description The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differ

3.3V ECL 첨2/4, 첨4/6 Clock Generation Chip

Description The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differ

3.3V ECL 첨2/4, 첨4/6 Clock Generation Chip

Description The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differ

3.3/5VECL Differential Phase?묯requency Detector

Description The MC100LVEL40 is a three state phase frequency−detector intended for phase−locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rat

Phase-Frequency Detector

Description The MC100LVEL40 is a three state phase frequency−detector intended for phase−locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rat

3.3/5VECL Differential Phase?묯requency Detector

Description The MC100LVEL40 is a three state phase frequency−detector intended for phase−locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rat

Differential Clock D Flip-Flop

Description The MC100LVEL51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 device, but operates from a 3.3 V supply. With propagation delays and output transition times essentially equal to the EL51, the LVEL51 is ideally suited for those applica

Differential Clock D Flip-Flop

Description The MC100LVEL51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 device, but operates from a 3.3 V supply. With propagation delays and output transition times essentially equal to the EL51, the LVEL51 is ideally suited for those applica

Differential Clock D Flip-Flop

Description The MC100LVEL51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 device, but operates from a 3.3 V supply. With propagation delays and output transition times essentially equal to the EL51, the LVEL51 is ideally suited for those applica

Dual Differential 2:1 Multiplexer

Description The MC100LVEL56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. The device features both individual and common select inputs to address both data path and random logic ap

2:1 Multiplexer

Description The MC100LVEL58 is a 2:1 multiplexer. The device is pin and functionally equivalent to the EL58 and works from a 3.3 V supply. With AC performance similar to the EL58 device, the LVEL58 is ideal for low voltage applications which require the ultimate in AC performance. Features • 44

2:1 Multiplexer

Description The MC100LVEL58 is a 2:1 multiplexer. The device is pin and functionally equivalent to the EL58 and works from a 3.3 V supply. With AC performance similar to the EL58 device, the LVEL58 is ideal for low voltage applications which require the ultimate in AC performance. Features • 44

2:1 Multiplexer

Description The MC100LVEL58 is a 2:1 multiplexer. The device is pin and functionally equivalent to the EL58 and works from a 3.3 V supply. With AC performance similar to the EL58 device, the LVEL58 is ideal for low voltage applications which require the ultimate in AC performance. Features • 44

Triple 2:1 Multiplexer

Description The MC100LVEL59 is a 3.3 V triple 2:1 multiplexer with differential outputs. The output data of the multiplexers can be controlled individually via the select inputs or as a group via the common select input. The flexible selection scheme makes the device useful for both data path and

Triple ECL to PECL Translator

Description The MC100LVEL90 is a triple ECL to LVPECL translator. The device receives either −3.3 V or −5 V differential ECL signals, determined by the VEE supply level, and translates them to +3.3 V differential LVPECL output signals. Features • 500 ps Propagation Delays • ESD Protection: >2

Triple PECL to ECL Translator?

Description The MC100LVEL91 is a triple LVPECL input to ECL output translator. The device receives low voltage differential PECL signals, determined by the VCC supply level, and translates them to differential −3.3 V to −5.0 V ECL output signals. To accomplish the level translation the LVEL91 re

Clock Management Design Using Low Skew and Low Jitter Devices

Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv