첨2 Divider

Description The MC100LVEL32 is an integrated ÷2 divider. The LVEL32 is functionally identical to the EL32, but operates from a 3.3 V supply. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random state; the reset allows for the

3.3 V ECL ÷2 Divider

The MC100LVEL32 is an integrated w2 divider. The LVEL32 is functionally identical to the EL32, but operates from a 3.3 V supply.The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random state; the reset allows for the synchronization • 510ps Propagation Delay\n• 2.6 GHz Typical Maximum Frequency\n• ESD Protection: >4 KV HBM, >200 V MM\n• The 100 Series Contains Temperature Compensation\n• PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE= 0 V\n• NECL Mode Operating Range: VCC= 0 V with VEE = -3.0 V to -3.8 V\n• Internal In;

3.3V ECL 첨2 Divider

文件：140.57 Kbytes Page：8 Pages

첨2 Divider

Description The MC100LVEL32 is an integrated ÷2 divider. The LVEL32 is functionally identical to the EL32, but operates from a 3.3 V supply. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random state; the reset allows for the

첨2 Divider

Description The MC100LVEL32 is an integrated ÷2 divider. The LVEL32 is functionally identical to the EL32, but operates from a 3.3 V supply. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random state; the reset allows for the

3.3V ECL 첨2 Divider

文件：140.57 Kbytes Page：8 Pages

3.3 V ECL /2 Divider

文件：167.37 Kbytes Page：8 Pages

3.3V ECL 첨2 Divider

文件：140.57 Kbytes Page：8 Pages

Evaluation Board Manual for High Frequency SOIC 8

文件：202.47 Kbytes Page：20 Pages

3.3V ECL 첨2 Divider

文件：140.57 Kbytes Page：8 Pages

3.3 V ECL /2 Divider

文件：167.37 Kbytes Page：8 Pages

3.3V ECL 첨2 Divider

文件：140.57 Kbytes Page：8 Pages

3.3 V ECL /2 Divider

文件：167.37 Kbytes Page：8 Pages

3.3V ECL 첨2 Divider

文件：140.57 Kbytes Page：8 Pages

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DIVIDER DIV X2 3.3V 8-SOIC 集成电路（IC） 计数器，除法器

封装/外壳：8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 包装：管件 描述：IC DIVIDER DIV X2 ECL DFF 8TSSOP 集成电路（IC） 计数器，除法器

3.3V ECL 첨2 Divider

文件：140.57 Kbytes Page：8 Pages

3.3V ECL 첨2 Divider

文件：140.57 Kbytes Page：8 Pages

3.3 V ECL /2 Divider

文件：167.37 Kbytes Page：8 Pages

3.3V ECL 첨2 Divider

文件：140.57 Kbytes Page：8 Pages

3.3 V ECL /2 Divider

文件：167.37 Kbytes Page：8 Pages

3.3V ECL 첨2 Divider

文件：140.57 Kbytes Page：8 Pages

3.3V ECL 첨2 Divider

文件：140.57 Kbytes Page：8 Pages

3.3V ECL 첨2 Divider

文件：140.57 Kbytes Page：8 Pages

3.3 V ECL /2 Divider

文件：167.37 Kbytes Page：8 Pages

ECL/PECL 첨 2 Divider

DESCRIPTION The AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple EL32’s in a system. The EL32 provides a VBB