Ultra Low-Power, Single/Dual-Supply Comparators

General Description The MAX921–MAX924 single, dual, and quad micropower, low-voltage comparators feature the lowest power consumption available. These comparators draw less than 4µA supply current over temperature (MAX921/MAX922), and include an internal 1.182V ±1 voltage reference, programmable

超低功耗、单/双电源比较器

Ultra Low-Power, Single/Dual-Supply Comparators

文件：192.13 Kbytes Page：17 Pages

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

Programmable DC-Balanced 21-Bit Serializers

General Description The MAX9209/MAX9213 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization. The MAX9209/MAX9213 feature programmable DC balance, which allows isolation between the serializ

Programmable DC-Balanced 21-Bit Serializers

General Description The MAX9209/MAX9213 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization. The MAX9209/MAX9213 feature programmable DC balance, which allows isolation between the serializ

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

Programmable DC-Balanced 21-Bit Serializers

General Description The MAX9209/MAX9213 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization. The MAX9209/MAX9213 feature programmable DC balance, which allows isolation between the serializ

Programmable DC-Balanced 21-Bit Serializers

General Description The MAX9209/MAX9213 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization. The MAX9209/MAX9213 feature programmable DC balance, which allows isolation between the serializ

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

Programmable DC-Balanced 21-Bit Serializers

General Description The MAX9209/MAX9213 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization. The MAX9209/MAX9213 feature programmable DC balance, which allows isolation between the serializ

Programmable DC-Balanced 21-Bit Serializers

General Description The MAX9209/MAX9213 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization. The MAX9209/MAX9213 feature programmable DC balance, which allows isolation between the serializ

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer

General Description The MAX9217 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial data stream. Eighteen bits of video data and 9 bits of control data are encoded and multiplexed onto the serial interface, reducing the serial data rate. The data enable in

27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer

General Description The MAX9217 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial data stream. Eighteen bits of video data and 9 bits of control data are encoded and multiplexed onto the serial interface, reducing the serial data rate. The data enable in

27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer

General Description The MAX9217 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial data stream. Eighteen bits of video data and 9 bits of control data are encoded and multiplexed onto the serial interface, reducing the serial data rate. The data enable in

27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer

General Description The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel

27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer

General Description The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel

27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer

General Description The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel

Ultra Low-Power, Single/Dual-Supply Comparators

General Description The MAX921–MAX924 single, dual, and quad micropower, low-voltage comparators feature the lowest power consumption available. These comparators draw less than 4µA supply current over temperature (MAX921/MAX922), and include an internal 1.182V ±1 voltage reference, programmable

Ultra Low-Power, Single/Dual-Supply Comparators

General Description The MAX921–MAX924 single, dual, and quad micropower, low-voltage comparators feature the lowest power consumption available. These comparators draw less than 4µA supply current over temperature (MAX921/MAX922), and include an internal 1.182V ±1 voltage reference, programmable

Ultra Low-Power, Single/Dual-Supply Comparators

General Description The MAX921–MAX924 single, dual, and quad micropower, low-voltage comparators feature the lowest power consumption available. These comparators draw less than 4µA supply current over temperature (MAX921/MAX922), and include an internal 1.182V ±1 voltage reference, programmable

Ultra Low-Power, Single/Dual-Supply Comparators

General Description The MAX921–MAX924 single, dual, and quad micropower, low-voltage comparators feature the lowest power consumption available. These comparators draw less than 4µA supply current over temperature (MAX921/MAX922), and include an internal 1.182V ±1% voltage reference, programm

Ultra Low-Power, Single/Dual-Supply Comparators

General Description The MAX921–MAX924 single, dual, and quad micropower, low-voltage comparators feature the lowest power consumption available. These comparators draw less than 4µA supply current over temperature (MAX921/MAX922), and include an internal 1.182V ±1 voltage reference, programmable

Ultra Low-Power, Single/Dual-Supply Comparators

General Description The MAX921–MAX924 single, dual, and quad micropower, low-voltage comparators feature the lowest power consumption available. These comparators draw less than 4µA supply current over temperature (MAX921/MAX922), and include an internal 1.182V ±1 voltage reference, programmable

Ultra Low-Power, Single/Dual-Supply Comparators

General Description The MAX921–MAX924 single, dual, and quad micropower, low-voltage comparators feature the lowest power consumption available. These comparators draw less than 4µA supply current over temperature (MAX921/MAX922), and include an internal 1.182V ±1 voltage reference, programmable

Ultra Low-Power, Single/Dual-Supply Comparators

General Description The MAX921–MAX924 single, dual, and quad micropower, low-voltage comparators feature the lowest power consumption available. These comparators draw less than 4µA supply current over temperature (MAX921/MAX922), and include an internal 1.182V ±1 voltage reference, programmable

Ultra Low-Power, Single/Dual-Supply Comparators

General Description The MAX921–MAX924 single, dual, and quad micropower, low-voltage comparators feature the lowest power consumption available. These comparators draw less than 4µA supply current over temperature (MAX921/MAX922), and include an internal 1.182V ±1 voltage reference, programmable

Ultra Low-Power, Single/Dual-Supply Comparators

文件：192.13 Kbytes Page：17 Pages

Programmable DC-Balance 21-Bit Deserializers

文件：194.64 Kbytes Page：17 Pages

Programmable DC-Balance 21-Bit Deserializers

文件：1.29449 Mbytes Page：17 Pages

Programmable DC-Balance 21-Bit Deserializers

文件：194.64 Kbytes Page：17 Pages

Programmable DC-Balance 21-Bit Deserializers

文件：1.29449 Mbytes Page：17 Pages

Programmable DC-Balance 21-Bit Deserializers

文件：194.64 Kbytes Page：17 Pages

Programmable DC-Balance 21-Bit Deserializers

文件：1.29449 Mbytes Page：17 Pages

封装/外壳：48-TFSOP（0.240"，6.10mm 宽） 功能：解串器 包装：卷带（TR） 描述：IC DESERIALIZER PROG 48TSSOP 集成电路（IC） 串行器，解串器

Programmable DC-Balanced 21-Bit Serializers

文件：319.8 Kbytes Page：20 Pages

Programmable DC-Balanced 21-Bit Serializers

文件：319.8 Kbytes Page：20 Pages

Programmable DC-Balanced 21-Bit Serializers

文件：321.62 Kbytes Page：21 Pages

Programmable DC-Balanced 21-Bit Serializers

文件：319.8 Kbytes Page：20 Pages

Programmable DC-Balanced 21-Bit Serializers

文件：597 Kbytes Page：18 Pages

封装/外壳：48-WFQFN 裸露焊盘 功能：串行器 包装：卷带（TR） 描述：PROGRAMMABLE DC-BALANCED 21-BIT 集成电路（IC） 串行器，解串器

Programmable DC-Balanced 21-Bit Serializers

文件：319.8 Kbytes Page：20 Pages

Programmable DC-Balanced 21-Bit Serializers

文件：321.62 Kbytes Page：21 Pages

Programmable DC-Balanced 21-Bit Serializers

文件：597 Kbytes Page：18 Pages

Programmable DC-Balance 21-Bit Deserializers

文件：1.29449 Mbytes Page：17 Pages

Programmable DC-Balance 21-Bit Deserializers

文件：1.29449 Mbytes Page：17 Pages

Programmable DC-Balance 21-Bit Deserializers

文件：194.64 Kbytes Page：17 Pages

Programmable DC-Balanced 21-Bit Serializers

文件：319.8 Kbytes Page：20 Pages

Programmable DC-Balanced 21-Bit Serializers

文件：319.8 Kbytes Page：20 Pages

Fully Assembled and Tested

文件：1.43721 Mbytes Page：12 Pages

27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer

文件：172.31 Kbytes Page：15 Pages