Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

Short-Loop Ringing SLIC with Ground Start

Introduction The Agere Systems Inc. L9216 is a subscriber line interface circuit (SLIC) that is optimized for shortloop, power-sensitive applications. This device provides the complete set of line interface functionality, including power ringing needed to interface to a subscriber loop. This devi

Short-Loop Ringing SLIC with Ground Start

Introduction The Agere Systems Inc. L9216 is a subscriber line interface circuit (SLIC) that is optimized for shortloop, power-sensitive applications. This device provides the complete set of line interface functionality, including power ringing needed to interface to a subscriber loop. This devi

Short-Loop Ringing SLIC with Ground Start

Introduction The Agere Systems Inc. L9216 is a subscriber line interface circuit (SLIC) that is optimized for shortloop, power-sensitive applications. This device provides the complete set of line interface functionality, including power ringing needed to interface to a subscriber loop. This devi

Silicon NPN epitaxial planer transistor

For digital circuits ■ Features ● Costs can be reduced through downsizing of the equipment and reduction of the number of parts. ● SS-Mini type package, allowing automatic insertion through tape packing and magazine packing.

HIGH SPEED PLL FOR DTS

文件：940.44 Kbytes Page：22 Pages