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型号	功能描述	生产厂家企业	LOGO
K4H510438	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	SAMSUNG 三星	SAMSUNG
K4H510438A-TCA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438A-TCA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438A-TCB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438A-TLA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438A-TLA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438A-TLB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438B-TC/LA2	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	SAMSUNG 三星	SAMSUNG
K4H510438B-TC/LB0	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	SAMSUNG 三星	SAMSUNG
K4H510438B-TC/LB3	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	SAMSUNG 三星	SAMSUNG
K4H510438B-TCA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438B-TCA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438B-TCB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438B-TCSLASHLA2	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	SAMSUNG 三星	SAMSUNG
K4H510438B-TCSLASHLB0	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	SAMSUNG 三星	SAMSUNG
K4H510438B-TCSLASHLB3	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	SAMSUNG 三星	SAMSUNG
K4H510438B-TLA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438B-TLA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438B-TLB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438B-UC/LA2	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	SAMSUNG 三星	SAMSUNG
K4H510438B-UC/LB0	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	SAMSUNG 三星	SAMSUNG
K4H510438B-UC/LB3	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	SAMSUNG 三星	SAMSUNG
K4H510438B-UCSLASHLA2	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	SAMSUNG 三星	SAMSUNG
K4H510438B-UCSLASHLB0	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	SAMSUNG 三星	SAMSUNG
K4H510438B-UCSLASHLB3	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	SAMSUNG 三星	SAMSUNG
K4H510438C-TCA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438C-TCA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438C-TCB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438C-TLA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438C-TLA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438C-TLB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438D	DDR SDRAM Product Guide Consumer Memory	SAMSUNG 三星	SAMSUNG
K4H510438D	512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	SAMSUNG 三星	SAMSUNG
K4H510438D-TCA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438D-TCA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438D-TCB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438D-TLA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438D-TLA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438D-TLB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438D-UC/LA2	512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	SAMSUNG 三星	SAMSUNG
K4H510438D-UC/LB0	512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	SAMSUNG 三星	SAMSUNG
K4H510438D-UCSLASHLA2	512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	SAMSUNG 三星	SAMSUNG
K4H510438D-UCSLASHLB0	512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	SAMSUNG 三星	SAMSUNG
K4H510438E-TCA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438E-TCA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438E-TCB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438E-TLA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438E-TLA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438E-TLB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	SAMSUNG 三星	SAMSUNG
K4H510438F	512Mb F-die DDR SDRAM Specification Consumer Memory	SAMSUNG 三星	SAMSUNG
K4H510438F	Consumer Memory SDRAM Product Guide Memory Division November 2007	SAMSUNG 三星	SAMSUNG
K4H510438F-LC/LB0	512Mb F-die DDR SDRAM Specification Consumer Memory	SAMSUNG 三星	SAMSUNG
K4H510438F-LC/LB3	512Mb F-die DDR SDRAM Specification Consumer Memory	SAMSUNG 三星	SAMSUNG
K4H510438F-LCSLASHLB0	512Mb F-die DDR SDRAM Specification Consumer Memory	SAMSUNG 三星	SAMSUNG
K4H510438F-LCSLASHLB3	512Mb F-die DDR SDRAM Specification Consumer Memory	SAMSUNG 三星	SAMSUNG
K4H510438G	Consumer Memory SDRAM Product Guide Memory Division November 2007	SAMSUNG 三星	SAMSUNG
K4H510438G	512Mb G-die DDR SDRAM Specification General Description The K4H510438G / K4H510838G / K4H511638G is 536,870,912 bits of double data rate synchronous DRAM organized as 4x 33,554,432 / 4x 16,777,216 / 4x 8,388,608 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe al	SAMSUNG 三星	SAMSUNG
K4H510438G-LC/LB0	512Mb G-die DDR SDRAM Specification General Description The K4H510438G / K4H510838G / K4H511638G is 536,870,912 bits of double data rate synchronous DRAM organized as 4x 33,554,432 / 4x 16,777,216 / 4x 8,388,608 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe al	SAMSUNG 三星	SAMSUNG
K4H510438G-LC/LB3	512Mb G-die DDR SDRAM Specification General Description The K4H510438G / K4H510838G / K4H511638G is 536,870,912 bits of double data rate synchronous DRAM organized as 4x 33,554,432 / 4x 16,777,216 / 4x 8,388,608 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe al	SAMSUNG 三星	SAMSUNG
K4H510438G-LCSLASHLB0	512Mb G-die DDR SDRAM Specification General Description The K4H510438G / K4H510838G / K4H511638G is 536,870,912 bits of double data rate synchronous DRAM organized as 4x 33,554,432 / 4x 16,777,216 / 4x 8,388,608 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe al	SAMSUNG 三星	SAMSUNG

K4H510438产品属性

类型
描述
型号
K4H510438
制造商
SAMSUNG
制造商全称
Samsung semiconductor
功能描述
512Mb B-die DDR SDRAM Specification

K4H510438供应商更多...

更新时间：2026-3-1 17:00:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市得捷芯城科技有限公司	K4H510438D-UCB3	SAMSUNG(三星)	25+	N/A	21000	原装正品现货,原厂订货,可支持含税原型号开票。	询价
深圳市华斯顿科技有限公司	K4H510438D-UCB3	SAMSUNG	25+23+	TSSOP66	36634	绝对原装正品全新进口深圳现货	询价
深圳市胜彬电子有限公司	K4H510438G-LCB3	SAMSUNG	22+	TSOP-66	8000	原装正品支持实单	询价
深圳市威雅利发展有限公司	K4H510438G-LCB3	SAMSUNG	0113+	SSOP	843	一级代理,专注军工、汽车、医疗、工业、新能源、电力	询价
齐创科技(上海,北京,青岛)有限公司	K4H510438G-LCB3	SAMSUNG	23+	TSOP-66	5000	原装正品,假一罚十	询价
深圳市纳艾斯科技有限公司	K4H510438G-LCB3	SAMSUNG	24+	SSOP	80000	只做自己库存全新原装进口正品假一赔百可开13%增	询价
深圳市宇创芯科技有限公司	K4H510438G-HCCC	SAMSUNG/三星	24+	FBGA	9600	原装现货,优势供应,支持实单!	询价
深圳诚思涵科技有限公司	K4H510438C-ZCCC	SAMSUNG	18+	FBGA60	85600	保证进口原装可开17%增值税发票	询价
深圳市莱克讯科技有限公司	K4H510438B-TCB0	SAMSUNG	1923+	TSOP	9865	原装进口现货库存专业工厂研究所配单供货	询价
中天科工半导体（深圳）有限公司	K4H510438G-LCB3	SAMSUNG/三星	20+	TSOP	35830	原装优势主营型号-可开原型号增税票	询价

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K4S641632H-TC30，K4S641632H-UC6，K4SA160822DTC1H，K616V1002CT-12
2020-2-24
K4T1G084QJ-BCE7
K4T1G084QJ-BCE7
2019-10-28

DdatasheetPDF页码索引

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DdatasheetPDF页码索引