IS45S价格

参考价格:¥47.7338

型号:IS45S16160G-7CTLA1 品牌:ISSI 备注:这里有IS45S多少钱,2025年最近7天走势,今日出价,今日竞价,IS45S批发/采购报价,IS45S行情走势销售排行榜,IS45S报价。
型号 功能描述 生产厂家 企业 LOGO 操作

64M x 8, 32M x 16 512Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 512Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 512Mb SDRAM is organized as follows. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous;

ISSI

矽成半导体

64M x 8, 32M x 16 512Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 512Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 512Mb SDRAM is organized as follows. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous;

ISSI

矽成半导体

64M x 8, 32M x 16 512Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 512Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 512Mb SDRAM is organized as follows. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous;

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

ISSI

矽成半导体

512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

OVERVIEW ISSIs 64Mb Synchronous DRAM IS42/45S32200E is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. GENERAL DES

ISSI

矽成半导体

512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

OVERVIEW ISSIs 64Mb Synchronous DRAM IS42/45S32200E is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. GENERAL DES

ISSI

矽成半导体

512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

OVERVIEW ISSIs 64Mb Synchronous DRAM IS42/45S32200E is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. GENERAL DES

ISSI

矽成半导体

512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

OVERVIEW ISSIs 64Mb Synchronous DRAM IS42/45S32200E is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. GENERAL DES

ISSI

矽成半导体

512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

OVERVIEW ISSIs 64Mb Synchronous DRAM IS42/45S32200E is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. GENERAL DES

ISSI

矽成半导体

512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

OVERVIEW ISSIs 64Mb Synchronous DRAM IS42/45S32200E is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. GENERAL DES

ISSI

矽成半导体

512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

OVERVIEW ISSIs 64Mb Synchronous DRAM IS42/45S32200E is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. GENERAL DES

ISSI

矽成半导体

512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

OVERVIEW ISSIs 64Mb Synchronous DRAM IS42/45S32200E is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. GENERAL DES

ISSI

矽成半导体

512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

OVERVIEW ISSIs 64Mb Synchronous DRAM IS42/45S32200E is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. GENERAL DES

ISSI

矽成半导体

512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

OVERVIEW ISSIs 64Mb Synchronous DRAM IS42/45S32200E is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. GENERAL DES

ISSI

矽成半导体

4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

ISSI

矽成半导体

4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

ISSI

矽成半导体

4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

ISSI

矽成半导体

4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

ISSI

矽成半导体

4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

ISSI

矽成半导体

4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

ISSI

矽成半导体

4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

ISSI

矽成半导体

4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

ISSI

矽成半导体

4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

ISSI

矽成半导体

512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

文件:803.48 Kbytes Page:81 Pages

ISSI

矽成半导体

512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

文件:803.48 Kbytes Page:81 Pages

ISSI

矽成半导体

512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

文件:803.48 Kbytes Page:81 Pages

ISSI

矽成半导体

封装/外壳:60-TFBGA 包装:托盘 描述:IC DRAM 16MBIT PAR 60MINIBGA 集成电路(IC) 存储器

ETC

知名厂家

512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

文件:803.48 Kbytes Page:81 Pages

ISSI

矽成半导体

512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

文件:803.48 Kbytes Page:81 Pages

ISSI

矽成半导体

512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

文件:803.48 Kbytes Page:81 Pages

ISSI

矽成半导体

封装/外壳:50-TSOP(0.400",10.16mm 宽) 包装:托盘 描述:IC DRAM 16MBIT PAR 50TSOP II 集成电路(IC) 存储器

ETC

知名厂家

SDR SDRAM

ISSI

矽成半导体

512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM

文件:1.61909 Mbytes Page:82 Pages

ISSI

矽成半导体

512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM

文件:1.61909 Mbytes Page:82 Pages

ISSI

矽成半导体

512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM

文件:1.61909 Mbytes Page:82 Pages

ISSI

矽成半导体

512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM

文件:1.61909 Mbytes Page:82 Pages

ISSI

矽成半导体

512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM

文件:1.61909 Mbytes Page:82 Pages

ISSI

矽成半导体

512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM

文件:1.61909 Mbytes Page:82 Pages

ISSI

矽成半导体

Random column address every clock cycle

文件:1.66808 Mbytes Page:86 Pages

ISSI

矽成半导体

SDR SDRAM

ISSI

矽成半导体

SDR SDRAM

ISSI

矽成半导体

256 Mb Single Data Rate Synchronous DRAM

文件:1.59869 Mbytes Page:40 Pages

ISSI

矽成半导体

256 Mb Single Data Rate Synchronous DRAM

文件:1.59869 Mbytes Page:40 Pages

ISSI

矽成半导体

256 Mb Single Data Rate Synchronous DRAM

文件:1.59869 Mbytes Page:40 Pages

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM

文件:1.05062 Mbytes Page:63 Pages

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM

文件:1.05062 Mbytes Page:63 Pages

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM

文件:1.05062 Mbytes Page:63 Pages

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM

文件:1.05062 Mbytes Page:63 Pages

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM

文件:1.05062 Mbytes Page:63 Pages

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM

文件:1.05062 Mbytes Page:63 Pages

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM

文件:1.05062 Mbytes Page:63 Pages

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM

文件:1.05062 Mbytes Page:63 Pages

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM

文件:1.05062 Mbytes Page:63 Pages

ISSI

矽成半导体

IS45S产品属性

  • 类型

    描述

  • 型号

    IS45S

  • 制造商

    IDEC Corporation

  • 功能描述

    SENS.IND. 10-30VDC PNP NC

更新时间:2025-11-19 17:55:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
ISSI
22+
SOP54
12245
现货,原厂原装假一罚十!
ISSI
三年内
1983
只做原装正品
ISSI/矽成
1712
SDRAM-AUTO/32MX16SD/TSOP
1
原装香港现货真实库存。低价
ISSI, Integrated Silicon Solut
24+
54-TSOP II
56200
一级代理/放心采购
ISSI
25+
TSOP54
3850
百分百原装正品 真实公司现货库存 本公司只做原装 可
ISSI Integrated Silicon Soluti
22+
54TSOP II
9000
原厂渠道,现货配单
ISSI
23+
TSOP54
4784
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、
ISSI, Integrated Silicon Solu
23+
54-TSOP II
7300
专注配单,只做原装进口现货
ISSI
1342
554
原装正品
ISSI Integrated Silicon Solut
25+
54-TSOP(0.400 10.16mm 宽)
9350
独立分销商 公司只做原装 诚心经营 免费试样正品保证

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