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IS45价格

参考价格:¥47.7338

型号:IS45S16160G-7CTLA1 品牌:ISSI 备注:这里有IS45多少钱,2026年最近7天走势,今日出价,今日竞价,IS45批发/采购报价,IS45行情走势销售排行榜,IS45报价。
型号 功能描述 生产厂家 企业 LOGO 操作

OPIC LIGHT DETECTOR WITH BULLT-IN SIGNAL PROCESSING CIRCULT FOR LIGHT MODULATION SYSTEM

OPIC Light Detector with Built-In Signal Processing Circuit for Light Modulation System Applications 1. Optoelectronic switches 2. Copiers, printers, facsimiles

SHARPSharp Corporation

夏普

LINEAR OUTPUT TYPE OPIC LIGHT DETECTOR

■ Features 1. Liner output 2. Two package according to mounting method Side-view type (IS445) Top-view type (IS455) 3. Capable of output voltage level adjustment due to external resistor ■ Applications 1. Copiers

SHARPSharp Corporation

夏普

Linear Output Type OPIC Light Detector

■ Features 1. Liner output 2. Two package according to mounting method Side-view type (IS445) Top-view type (IS455) 3. Capable of output voltage level adjustment due to external resistor ■ Applications 1. Copiers

SHARPSharp Corporation

夏普

High Speed Response Type OPIC Light Detector

■ Features 1. High speed response (t PHL : TYP.230ns ) 2. Uses a pattern to allow for possible positional deviation of the semiconductor laser spot. 3. Compact, mini-flat package ■ Applications 1. Laser beam printers

SHARPSharp Corporation

夏普

High Speed Response Type OPIC Light Detector

■ Features 1. High speed response type (t PHL: TYP. 300ns) 2. Pattern with semiconductor laser spot positional deviation taken into consideration (Detector size : 0.5mm x 3.0mm ) 3. Open collector output 4. Angle adjustment by means of outer mounting resistance ■ Applications 1. Laser beam

SHARPSharp Corporation

夏普

4M x 16Bits x 4Banks Mobile Synchronous DRAM

Features •JEDEC standard 3.3V, 2.5V, 1.8V power supply. •Auto refresh and self refresh. •All pins are compatible with LVCMOS interface. •8K refresh cycle / 64ms. •Programmable Burst Length and Burst Type. - 1, 2, 4, 8 or Full Page for Sequential Burst. - 4 or 8 for Interleave Burst. •Program

ISSI

矽成半导体

4M x 16Bits x 4Banks Mobile Synchronous DRAM

Features •JEDEC standard 3.3V, 2.5V, 1.8V power supply. •Auto refresh and self refresh. •All pins are compatible with LVCMOS interface. •8K refresh cycle / 64ms. •Programmable Burst Length and Burst Type. - 1, 2, 4, 8 or Full Page for Sequential Burst. - 4 or 8 for Interleave Burst. •Program

ISSI

矽成半导体

4M x 16Bits x 4Banks Mobile Synchronous DRAM

Features •JEDEC standard 3.3V, 2.5V, 1.8V power supply. •Auto refresh and self refresh. •All pins are compatible with LVCMOS interface. •8K refresh cycle / 64ms. •Programmable Burst Length and Burst Type. - 1, 2, 4, 8 or Full Page for Sequential Burst. - 4 or 8 for Interleave Burst. •Program

ISSI

矽成半导体

4M x 16Bits x 4Banks Mobile Synchronous DRAM

Features •JEDEC standard 3.3V, 2.5V, 1.8V power supply. •Auto refresh and self refresh. •All pins are compatible with LVCMOS interface. •8K refresh cycle / 64ms. •Programmable Burst Length and Burst Type. - 1, 2, 4, 8 or Full Page for Sequential Burst. - 4 or 8 for Interleave Burst. •Program

ISSI

矽成半导体

1M x 16Bits x 2Banks Low Power Synchronous DRAM

Features • JEDEC standard 3.3V, 2.5V, 1.8V power supply • Auto refresh and self refresh • All pins are compatible with LVCMOS interface • 4K refresh cycle / 64ms • Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full Page for Sequential Burst - 4 or 8 for Interleave Burst • Progra

ISSI

矽成半导体

1M x 16Bits x 2Banks Low Power Synchronous DRAM

Features • JEDEC standard 3.3V, 2.5V, 1.8V power supply • Auto refresh and self refresh • All pins are compatible with LVCMOS interface • 4K refresh cycle / 64ms • Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full Page for Sequential Burst - 4 or 8 for Interleave Burst • Progra

ISSI

矽成半导体

1M x 16Bits x 4Banks Mobile Synchronous DRAM

Features • JEDEC standard 3.3V, 2.5V, 1.8V power supply • Auto refresh and self refresh • All pins are compatible with LVCMOS interface • 4K refresh cycle / 64ms • Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full Page for Sequential Burst - 4 or 8 for Interleave Burst • Progra

ISSI

矽成半导体

1M x 16Bits x 4Banks Mobile Synchronous DRAM

Features • JEDEC standard 3.3V, 2.5V, 1.8V power supply • Auto refresh and self refresh • All pins are compatible with LVCMOS interface • 4K refresh cycle / 64ms • Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full Page for Sequential Burst - 4 or 8 for Interleave Burst • Progra

ISSI

矽成半导体

2M x 16Bits x 4Banks Mobile Synchronous DRAM

Features • JEDEC standard 3.3V, 2.5V, 1.8V power supply • Auto refresh and self refresh • All pins are compatible with LVCMOS interface • 4K refresh cycle / 64ms • Programmable Burst Length and Burst Type • 1, 2, 4, 8 or Full Page for Sequential Burst • 4 or 8 for Interleave Burst • Progra

ISSI

矽成半导体

2M x 16Bits x 4Banks Mobile Synchronous DRAM

Features • JEDEC standard 3.3V, 2.5V, 1.8V power supply • Auto refresh and self refresh • All pins are compatible with LVCMOS interface • 4K refresh cycle / 64ms • Programmable Burst Length and Burst Type • 1, 2, 4, 8 or Full Page for Sequential Burst • 4 or 8 for Interleave Burst • Progra

ISSI

矽成半导体

512K x 32Bits x 2Banks Low Power Synchronous DRAM

Features • JEDEC standard 3.3V, 2.5V, 1.8V power supply. • Auto refresh and self refresh. • All pins are compatible with LVCMOS interface. • 4K refresh cycle / 64ms. • Programmable Burst Length and Burst Type. - 1, 2, 4, 8 or Full Page for Sequential Burst. - 4 or 8 for Interleave Burst. •

ISSI

矽成半导体

512K x 32Bits x 2Banks Low Power Synchronous DRAM

Features • JEDEC standard 3.3V, 2.5V, 1.8V power supply. • Auto refresh and self refresh. • All pins are compatible with LVCMOS interface. • 4K refresh cycle / 64ms. • Programmable Burst Length and Burst Type. - 1, 2, 4, 8 or Full Page for Sequential Burst. - 4 or 8 for Interleave Burst. •

ISSI

矽成半导体

512K x 32Bits x 4Banks Mobile Synchronous DRAM

Features • JEDEC standard 3.3V, 2.5V, 1.8V power supply • Auto refresh and self refresh • All pins are compatible with LVCMOS interface • 4K refresh cycle / 64ms • Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full Page for Sequential Burst - 4 or 8 for Interleave Burst • Progra

ISSI

矽成半导体

512K x 32Bits x 4Banks Mobile Synchronous DRAM

Features • JEDEC standard 3.3V, 2.5V, 1.8V power supply • Auto refresh and self refresh • All pins are compatible with LVCMOS interface • 4K refresh cycle / 64ms • Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full Page for Sequential Burst - 4 or 8 for Interleave Burst • Progra

ISSI

矽成半导体

1M x 32Bits x 4Banks Mobile Synchronous DRAM

Features • JEDEC standard 3.3V, 2.5V, 1.8V power supply • Auto refresh and self refresh • All pins are compatible with LVCMOS interface • 4K refresh cycle / 64ms • Programmable Burst Length and Burst Type • 1, 2, 4, 8 or Full Page for Sequential Burst • 4 or 8 for Interleave Burst • Progra

ISSI

矽成半导体

1M x 32Bits x 4Banks Mobile Synchronous DRAM

Features • JEDEC standard 3.3V, 2.5V, 1.8V power supply • Auto refresh and self refresh • All pins are compatible with LVCMOS interface • 4K refresh cycle / 64ms • Programmable Burst Length and Burst Type • 1, 2, 4, 8 or Full Page for Sequential Burst • 4 or 8 for Interleave Burst • Progra

ISSI

矽成半导体

2M x 32Bits x 4Banks Mobile Synchronous DRAM

Features • JEDEC standard 3.3V, 2.5V, 1.8V power supply. • Auto refresh and self refresh. • All pins are compatible with LVCMOS interface. • 4K refresh cycle every 16ms (A2 grade) or 64 ms (Industrial, A1 grade). • Programmable Burst Length and Burst Type. - 1, 2, 4, 8 or Full Page for Sequ

ISSI

矽成半导体

2M x 32Bits x 4Banks Mobile Synchronous DRAM

Features • JEDEC standard 3.3V, 2.5V, 1.8V power supply. • Auto refresh and self refresh. • All pins are compatible with LVCMOS interface. • 4K refresh cycle every 16ms (A2 grade) or 64 ms (Industrial, A1 grade). • Programmable Burst Length and Burst Type. - 1, 2, 4, 8 or Full Page for Sequ

ISSI

矽成半导体

2M x 32Bits x 4Banks Mobile Synchronous DRAM

Features • JEDEC standard 3.3V, 2.5V, 1.8V power supply. • Auto refresh and self refresh. • All pins are compatible with LVCMOS interface. • 4K refresh cycle every 16ms (A2 grade) or 64 ms (Industrial, A1 grade). • Programmable Burst Length and Burst Type. - 1, 2, 4, 8 or Full Page for Sequ

ISSI

矽成半导体

2M x 32Bits x 4Banks Mobile Synchronous DRAM

Features • JEDEC standard 3.3V, 2.5V, 1.8V power supply. • Auto refresh and self refresh. • All pins are compatible with LVCMOS interface. • 4K refresh cycle every 16ms (A2 grade) or 64 ms (Industrial, A1 grade). • Programmable Burst Length and Burst Type. - 1, 2, 4, 8 or Full Page for Sequ

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 200,166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 200,166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 200,166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 200,166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 200,166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 200,166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 200,166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 200,166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 200,166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 200,166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 200,166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

ISSI

矽成半导体

32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burs

ISSI

矽成半导体

64M x 8, 32M x 16 512Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 512Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 512Mb SDRAM is organized as follows. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous;

ISSI

矽成半导体

64M x 8, 32M x 16 512Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 512Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 512Mb SDRAM is organized as follows. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous;

ISSI

矽成半导体

64M x 8, 32M x 16 512Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 512Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 512Mb SDRAM is organized as follows. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous;

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

ISSI

矽成半导体

16Mx32, 32Mx16, 64Mx8 512Mb SDRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply: Vdd/Vddq = 2.3V-3.6V IS42/45SxxxxxD - Vdd/Vddq = 3.3V IS42/45RxxxxxD - Vdd/Vddq = 2.5 • LVTTL interface • Prog

ISSI

矽成半导体

16Mx8, 8Mx16 128Mb SYNCHRONOUS DRAM

FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply Vdd Vddq IS42/45S81600F 3.3V 3.3V IS42/45S16800F 3.3V 3.3V • LVTTL interface • Programmable burst length – (1

ISSI

矽成半导体

IS45产品属性

  • 类型

    描述

  • 存储器格式:

    DRAM

  • 技术:

    SDRAM - 移动

  • 存储容量:

    128Mb (8M x 16)

  • 时钟频率:

    133MHz

  • 访问时间:

    5.4ns

  • 存储器接口:

    并联

  • 电压 - 电源:

    1.7V ~ 1.95V

  • 工作温度:

    -40°C ~ 85°C(TA)

  • 安装类型:

    表面贴装

  • 封装/外壳:

    54-TFBGA

  • 供应商器件封装:

    54-TFBGA(8x8)

IS45数据表相关新闻