isc P-Channel MOSFET Transistor

• FEATURES • Static drain-source on-resistance: RDS(on)≤200mΩ(@VGS= -10V; ID= -8.4A) • Advanced trench process technology • 100 avalanche tested • Minimum Lot-to-Lot variations for robust device performance and reliable operation • APPLICATIONS • Fast switching application.

Advanced Process Technology

Description The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low intern

Power MOSFET(Vdss=-100V, Rds(on)=0.20ohm, Id=-14A)

VDSS = -100V RDS(on) = 0.20Ω ID = -14A Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design t

Advanced Process Technology Surface Mount

VDSS = -100V RDS(on) = 0.20Ω ID = -14A Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design t

Advanced Process Technology

VDSS = -100V RDS(on) = 0.20Ω ID = -14A Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design t

Advanced Process Technology

28 V/7 A Smart Motor Module

General Description The AOZ9530QV is an integrated half-bridge gate driver with smart functions. The device includes one half-bridge gate driver, capable of driving high-side and low-side N-channel MOSFETs. Using two AOZ9530QV for single phase motor driver and three AOZ9530QV for three phase

PCIX I/O System Clock Generator with EMI Control Features

Features • Dedicated clock buffer power pins for reduced noise, crosstalk and jitter • Input clock frequency of 25 MHz to 33.3 MHz • Output frequencies of XINx1, XINx2, XINx3 and XINx4 • Output grouped in two banks of five clocks each • One REF XIN clock output • SMBus clock control interfac

MACHINE SCREW PAN PHILLIPS 10-32

文件：130.87 Kbytes Page：1 Pages

4 CML Output, Low Jitter Clock Generator

文件：979.91 Kbytes Page：41 Pages

4 CML Output, Low Jitter Clock Generator

文件：979.91 Kbytes Page：41 Pages