N-Channel Power MOSFETs, 27 A, 60-100V

25A and 28A, 80V and 100V, 0.077 and 0.100 Ohm, N-Channel Power MOSFETs

Description These devices are n-channel, enhancement mode, power MOSFETs designed especially for high power, high speed applications, such as switching power supplies, UPS, AC and DC motor controls, relay and solenoid drivers and high energy pulse circuits. ● Low RDS(on) ● VGS Rated at ±20 V ●

N-Channel Power MOSFETs, 27 A, 60-100 V

Description These devices are n-channel, enhancement mode, power MOSFETs designed especially for high power, high speed applications, such as switching power supplies, UPS, AC and DC motor controls, relay and solenoid drivers and high energy pulse circuits. ● Low RDS(on) ● VGS Rated at ±20 V ●

isc N-Channel MOSFET Transistor

文件：45.15 Kbytes Page：2 Pages

Trans MOSFET N-CH 100V 28A 3-Pin(3+Tab) TO-220AB

TREK 542A

©2021 Advanced APPLICATIONS  Semiconductor  LCD  Electronic assembly  ESD-sensitive processes

CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b