型号 功能描述 生产厂家 企业 LOGO 操作
IDT74FCT88915TT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

IDT

封装/外壳:28-SSOP(0.209",5.30mm 宽) 包装:管件 描述:IC PLL CLK GENERATOR 28-SSOP 集成电路(IC) 时钟发生器,PLL,频率合成器

ETC

知名厂家

IC PLL CLK GENERATOR 28-SSOP

RENESAS

瑞萨

IDT74FCT88915TT产品属性

  • 类型

    描述

  • 型号

    IDT74FCT88915TT

  • 功能描述

    IC PLL CLK GENERATOR 28-SSOP

  • RoHS

  • 类别

    集成电路(IC) >> 时钟/计时 - 时钟发生器,PLL,频率合成器

  • 系列

    74FCT

  • 标准包装

    1,000

  • 系列

    -

  • 类型

    时钟/频率合成器,扇出分配

  • PLL

    -

  • 输入

    -

  • 输出

    -

  • 电路数

    - 比率 -

  • 输出

    - 差分 -

  • 输出

    - 频率 -

  • 最大

    -

  • 除法器/乘法器

    -

  • 电源电压

    -

  • 工作温度

    -

  • 安装类型

    表面贴装

  • 封装/外壳

    56-VFQFN 裸露焊盘

  • 供应商设备封装

    56-VFQFP-EP(8x8)

  • 包装

    带卷(TR)

  • 其它名称

    844S012AKI-01LFT

更新时间:2025-11-20 16:18:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
IDT
24+
PLCC
3000
全新原装现货 优势库存
IDT
2402+
PLCC28
8324
原装正品!实单价优!
IDT
24+
SSOP
2000
只做原装正品现货 欢迎来电查询15919825718
IDT
25+
20
全新原装!优势库存热卖中!
IDT
24+
PLCC28
47186
郑重承诺只做原装进口现货
IDT
25+23+
PLCC
34396
绝对原装正品全新进口深圳现货
IDT
25+
PLCC28
3200
全新原装、诚信经营、公司现货销售
22+
5000
只做原装鄙视假货15118075546
IDT
24+
原装
6980
原装现货,可开13%税票
IDT
NEW
28PLCC
9526
代理全系列销售,全新原装正品,价格优势,长期供应,量大可订

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