LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

封装/外壳：28-SSOP（0.209"，5.30mm 宽） 包装：管件 描述：IC PLL CLK GENERATOR 28-SSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

IC PLL CLK GENERATOR 28-SSOP

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting