3-to-8 line Decoder / Demultiplexers

Description The HD74LV138A is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. The conditions at the binary-select inputs and the three enable inputs select one of eight input lines. Two active-low and one active-h

3-to-8-line Decoder / Demultiplexer

Description The HD74LV138A has three binary select inputs in a 16 pin package. If the device is enabled these inputs determine which one of the eight normally high outputs will go low. Two active low and one active high enables are provided to ease the cascading of decoders. Low voltage and high-

3-to-8-line Decoder / Demultiplexer

Description The HD74LV138A has three binary select inputs in a 16 pin package. If the device is enabled these inputs determine which one of the eight normally high outputs will go low. Two active low and one active high enables are provided to ease the cascading of decoders. Low voltage and high-

3-to-8-line Decoder / Demultiplexer

Description The HD74LV138A has three binary select inputs in a 16 pin package. If the device is enabled these inputs determine which one of the eight normally high outputs will go low. Two active low and one active high enables are provided to ease the cascading of decoders. Low voltage and high-

3-to-8 line Decoder / Demultiplexers

3-to-8-line Decoder / Demultiplexer

文件：118.76 Kbytes Page：9 Pages

General-Purpose Logics

3-to-8-line Decoder / Demultiplexer

文件：118.76 Kbytes Page：9 Pages

General-Purpose Logics

3-to-8-line Decoder / Demultiplexer

文件：118.76 Kbytes Page：9 Pages

3-to-8 line decoder/demultiplexer; inverting

3-to-8 line decoder/multiplexer; inverting

DESCRIPTION The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT138. The 74LV138 accepts three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). FEATURES • Wide operatin

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74LV138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (Y1, Y2 and E3). Every output will be HIGH unless Y1 and Y2 are LOW and E3 is HIGH. This multiple enable fun

3-to-8 line decoder/demultiplexer; inverting

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

文件：649.05 Kbytes Page：18 Pages