Triple 3-input NOR Gates

Features • High Speed Operation: tpd = 10 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

Triple 3-input NOR Gates

Features • High Speed Operation: tpd = 10 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

Triple 3-input NOR Gates

Triple 3-input NOR Gates

Octal D-type Flip-Flops (with Clear)

Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low sta

Octal D-type Flip-Flops (with Clear)

Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low sta

Octal D-type Flip-Flops (with Clear)

Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established

Quad. S-R Latches

Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established

Octal D-type Flip-Flops (with Clear)

Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established

Octal D-type Flip-Flops (with Clear)

Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established

Triple 3-input NOR Gates

Features • High Speed Operation: tpd = 10 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

Triple 3-input NOR Gates

Features • High Speed Operation: tpd = 10 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

Triple 3-input NOR Gates

Features • High Speed Operation: tpd = 10 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

Octal D-type Flip-Flops (with Clear)

Octal D-type Flip-Flops (with Clear)

文件：152.56 Kbytes Page：10 Pages

Octal D-type Flip-Flops (with Clear)

文件：152.56 Kbytes Page：10 Pages

Octal D-type Flip-Flops (with Clear)

文件：152.56 Kbytes Page：10 Pages

Octal D-type Flip-Flops (with Clear)

文件：152.56 Kbytes Page：10 Pages

Octal D-type Flip-Flops (with Clear)

文件：152.56 Kbytes Page：10 Pages

SEMICONDUCTORS

文件：2.43533 Mbytes Page：31 Pages

High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V Function compatible with 54LS27 High Noise Immunity CMOS process.

Triple 3-input NOR gate

Triple 3-input NOR gate

GENERAL DESCRIPTION The 74HC/HCT27 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT27 provide the 3-input NOR function. FEATURES • Output capability: standard • ICC categor

Triple 3-input NOR gate

Triple 3-input NOR gate

文件：241.89 Kbytes Page：12 Pages