Octal D-type Flip-Flops (with Clear)

Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low sta

Octal D-type Flip-Flops (with Clear)

Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low sta

Octal D-type Flip-Flops (with Clear)

Octal D-type Flip-Flops (with Clear)

Octal D-type Flip-Flops (with Clear)

文件：152.56 Kbytes Page：10 Pages

Octal D-type Flip-Flops (with Clear)

文件：152.56 Kbytes Page：10 Pages

Octal D-type Flip-Flops (with Clear)

文件：152.56 Kbytes Page：10 Pages

General-Purpose Logics-HD/RD74HC Series

Octal D-type Flip-Flops (with Clear)

文件：152.56 Kbytes Page：10 Pages

Octal D-type Flip-Flops (with Clear)

文件：152.56 Kbytes Page：10 Pages

Octal D-type flip-flop with reset; positive-edge trigger

General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH c

Octal D Flip-Flop with Common Clock and Reset

The SL74HC273 is identical in pinout to the LS/ALS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of eight D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIG

Octal D Flip-Flop with Common Clock and Reset

Octal D Flip-Flop with Common Clock and Reset High−Performance Silicon−Gate CMOS The MC74HC273A is identical in pinout to the LS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of eight D flip−f

Octal D-type flip-flop with reset; positive-edge trigger