Triple 3-input NOR gate

GENERAL DESCRIPTION The 74HC/HCT27 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT27 provide the 3-input NOR function. FEATURES • Output capability: standard • ICC categor

Triple 3-input NOR gate

High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V Function compatible with 54LS27 High Noise Immunity CMOS process.

Triple 3-input NOR gate

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丝印代码：74HC273D；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • Octal D-Type Flip-Flop with Clear General The 74HC273D is a high speed CMOS OCTAL D-TYPE FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Infor

Octal D Flip-Flop with Common Clock and Reset

The SL74HC273 is identical in pinout to the LS/ALS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of eight D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIG

Octal D-type flip-flop with reset; positive-edge trigger

General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH c

Octal D Flip-Flop with Common Clock and Reset

The SL74HC273 is identical in pinout to the LS/ALS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of eight D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-

Octal D Flip-Flop with Common Clock and Reset

Octal D Flip-Flop with Common Clock and Reset High−Performance Silicon−Gate CMOS The MC74HC273A is identical in pinout to the LS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of eight D flip−f

Octal D-type flip-flop with reset; positive-edge trigger

The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A L • Input levels:• For 74HC273: CMOS level\n• For 74HCT273: TTL level\n\n• Common clock and master reset\n• Eight positive edge-triggered D-type flip-flops\n• Complies with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package;

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIG

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIG

Octal D-type flip-flop with reset; positive-edge trigger

General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH c

Octal D-type flip-flop with reset; positive-edge trigger

General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH c

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the

Octal D-type flip-flop with reset; positive-edge trigger

General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH c

Octal D-type flip-flop with reset; positive-edge trigger

General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH c

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIG

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the

Triple 3-input NOR gate

Triple 3-input NOR gate

1. General description The 74HC27-Q100; 74HCT27-Q100 is a triple 3-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standa

Triple 3-input NOR gate

Triple 3-input NOR gate

GENERAL DESCRIPTION The 74HC/HCT27 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT27 provide the 3-input NOR function. FEATURES • Output capability: standard • ICC categor

Triple 3-input NOR gate

Triple 3-input NOR gate

1. General description The 74HC27-Q100; 74HCT27-Q100 is a triple 3-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standa

Triple 3-input NOR gate

GENERAL DESCRIPTION The 74HC/HCT27 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT27 provide the 3-input NOR function. FEATURES • Output capability: standard • ICC categor

Triple 3-input NOR gate

Triple 3-input NOR gate

Triple 3-input NOR gate

1. General description The 74HC27-Q100; 74HCT27-Q100 is a triple 3-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standa

Triple 3-input NOR gate

1. General description The 74HC27-Q100; 74HCT27-Q100 is a triple 3-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standa

8 位 D 型清零端触发器

Octal D-type flip-flop with reset; positive-edge trigger

Octal D-type flip-flop with reset; positive-edge trigger

封装/外壳：20-VFQFN 裸露焊盘 功能：主复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 8BIT 20DHVQFN 集成电路（IC） 触发器

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 功能：主复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 8BIT 20SOIC 集成电路（IC） 触发器

Octal D-type flip-flop with reset; positive-edge trigger

Octal D-type flip-flop with reset; positive-edge trigger

Octal D-type flip-flop with reset; positive-edge trigger

Octal D-type flip-flop with reset; positive-edge trigger

Octal D-type flip-flop with reset; positive-edge trigger

Octal D-type flip-flop with reset; positive-edge trigger

Octal D-type flip-flop with reset; positive-edge trigger

Triple 3-input NOR gate

文件：241.89 Kbytes Page：12 Pages

Triple 3-input NOR gate

文件：703.84 Kbytes Page：15 Pages

Triple 3-input NOR gate

文件：241.89 Kbytes Page：12 Pages

Triple 3-input NOR gate

文件：703.84 Kbytes Page：15 Pages

Triple 3-input NOR gate

文件：241.89 Kbytes Page：12 Pages

Triple 3-input NOR gate

文件：703.84 Kbytes Page：15 Pages

Triple 3-input NOR gate

文件：703.84 Kbytes Page：15 Pages

TRIPLE 3-INPUT NOR GATE

DESCRIPTION The M54/74HC27 is a high speed CMOS TRIPLE 3-INPUT NOR GATE fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 7 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C ■ HIGH NOISE IMMUNITY VNIH = VNIL = 28 VCC (MIN.) ■ OUT

TRIPLE 3-INPUT NOR GATE

DESCRIPTION The M74HC27 is an high speed CMOS TRIPLE 3-INPUT NOR GATE fabricated with silicon gate C2MOS technology. ■ HIGH SPEED: tPD = 9ns (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETR