位置：首页 > IC中文资料第2776页 > DM74LS109
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
DM74LS109 | Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition t | FAIRCHILD 仙童半导体 |   | |
Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition t | FAIRCHILD 仙童半导体 | | ||
Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition t | FAIRCHILD 仙童半导体 | | ||
Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition t | FAIRCHILD 仙童半导体 | | ||
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs 文件：135 Kbytes Page：6 Pages | NSC 国半 | | ||
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs 文件：135 Kbytes Page：6 Pages | NSC 国半 | | ||
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs 文件：135 Kbytes Page：6 Pages | NSC 国半 | | ||
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs 文件：135 Kbytes Page：6 Pages | NSC 国半 | | ||
封装/外壳：16-DIP（0.300"，7.62mm） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16DIP 集成电路（IC） 触发器 | ONSEMI 安森美半导体 | | ||
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY The SN54/74LS109A consists of two high speed completely independent transition clocked JKflip-flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D flip-flop by | MOTOROLA 摩托罗拉 | | ||
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY The SN54/74LS109A consists of two high speed completely independent transition clocked JKflip-flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D flip-flop by | MOTOROLA 摩托罗拉 | | ||
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY The SN54/74LS109A consists of two high speed completely independent transition clocked JKflip-flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D flip-flop by | MOTOROLA 摩托罗拉 | |
| 替换型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
Dual J-K Positive-edge-triggered Flip-Flops(with Preset and Clear) | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI | | |
Ouadruple 2-input Positive NAND Gates | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI | | |
LOW POWER SCHOTTKY | ONSEMI 安森美半导体 | ONSEMI | | |
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
LOW POWER SCHOTTKY | ONSEMI 安森美半导体 | ONSEMI | | |
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP | MOTOROLA 摩托罗拉 | MOTOROLA | |
DM74LS109产品属性
- 类型
描述
- 型号
DM74LS109
- 功能描述
触发器 Dl J-K Flip-Flop
- RoHS
否
- 制造商
Texas Instruments
- 电路数量
2
- 逻辑系列
SN74
- 逻辑类型
D-Type Flip-Flop
- 极性
Inverting, Non-Inverting
- 输入类型
CMOS
- 传播延迟时间
4.4 ns
- 高电平输出电流
- 16 mA
- 低电平输出电流
16 mA
- 电源电压-最大
5.5 V
- 最大工作温度
+ 85 C
- 安装风格
SMD/SMT
- 封装/箱体
X2SON-8
- 封装
Reel
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
onsemi(安森美) |
25+ |
- |
18746 |
样件支持,可原厂排单订货! |
|||
NATIONALSEMI |
05+ |
原厂原装 |
6152 |
只做全新原装真实现货供应 |
|||
FSC/ON |
23+ |
原包装原封 □□ |
5147 |
原装进口特价供应 特价，原装元器件供应，支持开发样品 更多详细咨询 库存 |
|||
FAIR |
24+/25+ |
55 |
原装正品现货库存价优 |
||||
26+ |
N/A |
52000 |
一级代理-主营优势-实惠价格-不悔选择 |
||||
FAIRCHILD/仙童 |
25+ |
DIP16 |
90000 |
全新原装现货 |
|||
FSC |
24+ |
DIPSOP |
65200 |
一级代理/放心采购 |
|||
NS |
22+ |
DIP16 |
8000 |
原装正品支持实单 |
|||
NSC |
2016+ |
DIP |
3000 |
只做原装,假一罚十,公司可开17%增值税发票! |
|||
NS |
25+ |
DIP |
433 |
百分百原装正品 真实公司现货库存 本公司只做原装 可 |
DM74LS109规格书下载地址
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DM74LS109数据表相关新闻
DM54S574J/883C
DM54S574J/883C
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2020-7-10DM74LS241WM，DM74LS241WMX，DM74LS243N，DM74LS244N，DM74LS244SJX，DM74LS245N，DM74LS245SJX，DM74LS251M，DM74LS251MX，DM74LS251N，DM74LS253MX，DM74LS257BMX，DM74LS221MX，DM74LS221SJ，DM74LS221
DM74LS241WM，DM74LS241WMX，DM74LS243N，DM74LS244N，DM74LS244SJX，DM74LS245N，DM74LS245SJX，DM74LS251M，DM74LS251MX，DM74LS251N，DM74LS253MX，DM74LS257BMX，DM74LS221MX，DM74LS221SJ，DM74LS221
2019-12-18DM74AS169AN，P6KE200AT/B，UEP1H220MPD1TD，DM9328N，1N5232B(T50A)，LS3360L，LT1E53A，MC14511BDWR2，SMA020450100R1%A2，SAA1064T，DM74AS257M
DM74AS169AN，P6KE200AT/B，UEP1H220MPD1TD，DM9328N，1N5232B(T50A)，LS3360L，LT1E53A，MC14511BDWR2，SMA020450100R1%A2，SAA1064T，DM74AS257M
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2012-11-9
DdatasheetPDF页码索引
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