位置：首页 > IC中文资料第2776页 > DM74LS109AN
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
DM74LS109AN | Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition t | FAIRCHILD 仙童半导体 |   | |
DM74LS109AN | 封装/外壳：16-DIP（0.300"，7.62mm） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16DIP 集成电路（IC） 触发器 | ONSEMI 安森美半导体 | | |
DM74LS109AN | Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs 文件：135 Kbytes Page：6 Pages | NSC 国半 | | |
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs 文件：135 Kbytes Page：6 Pages | NSC 国半 | | ||
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs 文件：135 Kbytes Page：6 Pages | NSC 国半 | | ||
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY The SN54/74LS109A consists of two high speed completely independent transition clocked JKflip-flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D flip-flop by | MOTOROLA 摩托罗拉 | | ||
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY The SN54/74LS109A consists of two high speed completely independent transition clocked JKflip-flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D flip-flop by | MOTOROLA 摩托罗拉 | | ||
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY The SN54/74LS109A consists of two high speed completely independent transition clocked JKflip-flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D flip-flop by | MOTOROLA 摩托罗拉 | |
| 替换型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
Dual J-K Positive-edge-triggered Flip-Flops(with Preset and Clear) | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI | | |
Ouadruple 2-input Positive NAND Gates | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI | | |
LOW POWER SCHOTTKY | ONSEMI 安森美半导体 | ONSEMI | | |
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
LOW POWER SCHOTTKY | ONSEMI 安森美半导体 | ONSEMI | | |
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP | MOTOROLA 摩托罗拉 | MOTOROLA | |
DM74LS109AN产品属性
- 类型
描述
- 型号
DM74LS109AN
- 功能描述
触发器 Dl J-K Flip-Flop
- RoHS
否
- 制造商
Texas Instruments
- 电路数量
2
- 逻辑系列
SN74
- 逻辑类型
D-Type Flip-Flop
- 极性
Inverting, Non-Inverting
- 输入类型
CMOS
- 传播延迟时间
4.4 ns
- 高电平输出电流
- 16 mA
- 低电平输出电流
16 mA
- 电源电压-最大
5.5 V
- 最大工作温度
+ 85 C
- 安装风格
SMD/SMT
- 封装/箱体
X2SON-8
- 封装
Reel
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
onsemi |
25+ |
16-PDIP |
20948 |
样件支持,可原厂排单订货! |
|||
NS |
24+ |
DIP |
33487 |
郑重承诺只做原装进口现货 |
|||
onsemi |
25+ |
16-PDIP |
21000 |
正规渠道,免费送样。支持账期,BOM一站式配齐 |
|||
FSC |
0136+ |
DIP-16P |
1161 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
|||
FAIR |
24+/25+ |
55 |
原装正品现货库存价优 |
||||
NSC |
23+ |
原装原封 |
8888 |
专做原装正品,假一罚百! |
|||
NSC |
25+ |
10 |
公司优势库存 热卖中!! |
||||
FSC/MOT |
25+ |
DIP16 |
30000 |
代理全新原装现货,价格优势 |
|||
FAIRCILD |
22+ |
DIP-16 |
8000 |
原装正品支持实单 |
|||
NS |
97+ |
DIP |
369 |
全新 发货1-2天 |
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DM74LS109AN规格书下载地址
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DM74LS109AN数据表相关新闻
DM54S574J/883C
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2012-11-9
DdatasheetPDF页码索引
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