位置：首页 > IC中文资料第2776页 > DM74LS10
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
DM74LS10 | Triple 3-Input NAND Gate General Description This device contains three independent gates each of which performs the logic NAND function. | FAIRCHILD 仙童半导体 |   | |
DM74LS10 | Triple 3-Input NAND Gates 文件：120.85 Kbytes Page：6 Pages | NSC 国半 | | |
DM74LS10 | Triple 3-Input NAND Gate | ONSEMI 安森美半导体 | | |
Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition t | FAIRCHILD 仙童半导体 | | ||
Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition t | FAIRCHILD 仙童半导体 | | ||
Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition t | FAIRCHILD 仙童半导体 | | ||
Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition t | FAIRCHILD 仙童半导体 | | ||
Triple 3-Input NAND Gate General Description This device contains three independent gates each of which performs the logic NAND function. | FAIRCHILD 仙童半导体 | | ||
Triple 3-Input NAND Gate General Description This device contains three independent gates each of which performs the logic NAND function. | SYC | | ||
Triple 3-Input NAND Gate General Description This device contains three independent gates each of which performs the logic NAND function. | SYC | | ||
Triple 3-Input NAND Gate General Description This device contains three independent gates each of which performs the logic NAND function. | FAIRCHILD 仙童半导体 | | ||
Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs 文件：119.69 Kbytes Page：6 Pages | NSC 国半 | | ||
Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs 文件：119.69 Kbytes Page：6 Pages | NSC 国半 | | ||
Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs 文件：119.69 Kbytes Page：6 Pages | NSC 国半 | | ||
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs 文件：135 Kbytes Page：6 Pages | NSC 国半 | | ||
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs 文件：135 Kbytes Page：6 Pages | NSC 国半 | | ||
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs 文件：135 Kbytes Page：6 Pages | NSC 国半 | | ||
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs 文件：135 Kbytes Page：6 Pages | NSC 国半 | | ||
封装/外壳：16-DIP（0.300"，7.62mm） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16DIP 集成电路（IC） 触发器 | ONSEMI 安森美半导体 | | ||
Triple 3-Input NAND Gates 文件：120.85 Kbytes Page：6 Pages | NSC 国半 | | ||
Triple 3-Input NAND Gates 文件：120.85 Kbytes Page：6 Pages | NSC 国半 | | ||
Triple 3-Input NAND Gates 文件：120.85 Kbytes Page：6 Pages | NSC 国半 | | ||
Triple 3-Input NAND Gates 文件：120.85 Kbytes Page：6 Pages | NSC 国半 | | ||
封装/外壳：14-DIP（0.300"，7.62mm） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC GATE NAND 3CH 3-INP 14DIP 集成电路（IC） 门和反相器 | ONSEMI 安森美半导体 | | ||
Triple 3-Input NAND Gates 文件：120.85 Kbytes Page：6 Pages | NSC 国半 | | ||
TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE LOW POWER SCHOTTKY | MOTOROLA 摩托罗拉 | | ||
TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE LOW POWER SCHOTTKY | MOTOROLA 摩托罗拉 | |
| 替换型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
Dual J-K Positive-edge-triggered Flip-Flops(with Preset and Clear) | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI | | |
Ouadruple 2-input Positive NAND Gates | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI | | |
LOW POWER SCHOTTKY | ONSEMI 安森美半导体 | ONSEMI | | |
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
LOW POWER SCHOTTKY | ONSEMI 安森美半导体 | ONSEMI | | |
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP | MOTOROLA 摩托罗拉 | MOTOROLA | |
DM74LS10产品属性
- 类型
描述
- 型号
DM74LS10
- 功能描述
触发器 Dl J-K Flip-Flop
- RoHS
否
- 制造商
Texas Instruments
- 电路数量
2
- 逻辑系列
SN74
- 逻辑类型
D-Type Flip-Flop
- 极性
Inverting, Non-Inverting
- 输入类型
CMOS
- 传播延迟时间
4.4 ns
- 高电平输出电流
- 16 mA
- 低电平输出电流
16 mA
- 电源电压-最大
5.5 V
- 最大工作温度
+ 85 C
- 安装风格
SMD/SMT
- 封装/箱体
X2SON-8
- 封装
Reel
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
NS |
22+ |
DIP-14 |
8000 |
原装正品支持实单 |
|||
FSC |
1645+ |
SOP |
7500 |
只做原装进口,假一罚十 |
|||
NS |
22+ |
DIP14 |
30000 |
十七年VIP会员,诚信经营，一手货源，原装正品可零售！ |
|||
ON Semiconductor |
23+ |
7300 |
专注配单,只做原装进口现货 |
||||
NS(国半) |
25+ |
封装 |
500000 |
源自原厂成本,高价回收工厂呆滞 |
|||
NATIONALSEMI |
05+ |
原厂原装 |
6152 |
只做全新原装真实现货供应 |
|||
FSC/MOT |
25+ |
DIP16 |
30000 |
代理全新原装现货,价格优势 |
|||
FAIRCHILD |
NA |
8560 |
一级代理 原装正品假一罚十价格优势长期供货 |
||||
NS |
24+ |
DIP |
33487 |
郑重承诺只做原装进口现货 |
|||
FSC |
25+23+ |
DIP14 |
18583 |
绝对原装正品全新进口深圳现货 |
DM74LS10规格书下载地址
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- DM7473N
DM74LS10数据表相关新闻
DM54S574J/883C
DM54S574J/883C
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2020-7-10DM74LS241WM，DM74LS241WMX，DM74LS243N，DM74LS244N，DM74LS244SJX，DM74LS245N，DM74LS245SJX，DM74LS251M，DM74LS251MX，DM74LS251N，DM74LS253MX，DM74LS257BMX，DM74LS221MX，DM74LS221SJ，DM74LS221
DM74LS241WM，DM74LS241WMX，DM74LS243N，DM74LS244N，DM74LS244SJX，DM74LS245N，DM74LS245SJX，DM74LS251M，DM74LS251MX，DM74LS251N，DM74LS253MX，DM74LS257BMX，DM74LS221MX，DM74LS221SJ，DM74LS221
2019-12-18DM74AS169AN，P6KE200AT/B，UEP1H220MPD1TD，DM9328N，1N5232B(T50A)，LS3360L，LT1E53A，MC14511BDWR2，SMA020450100R1%A2，SAA1064T，DM74AS257M
DM74AS169AN，P6KE200AT/B，UEP1H220MPD1TD，DM9328N，1N5232B(T50A)，LS3360L，LT1E53A，MC14511BDWR2，SMA020450100R1%A2，SAA1064T，DM74AS257M
2019-12-8DM74ALS04BM-六反相器
DM74ALS04BM-六反相器，此装置包含6个独立的门，其中每个执行反向功能的逻辑。 特点 开关规格为50 pF 在整个温度开关规格保证和VCC范围 高级氧化隔离，离子注入肖特基TTL过程 功能和引脚对引脚兼容与肖特基和低功耗肖特基TTL对口 改进的AC性能超过肖特基二极管和低功耗肖特基同行 DM74ALS04BM：M14A 14引脚小外形集成电路（SOIC）,JEDEC MS- 012,0.150窄 DM74ALS04BSJ: M14D 14引脚小外形封装（SOP），
2012-11-9
DdatasheetPDF页码索引
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