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型号 功能描述 生产厂家 企业 LOGO 操作
DM74LS10

Triple 3-Input NAND Gate

General Description This device contains three independent gates each of which performs the logic NAND function.

FAIRCHILD

仙童半导体

DM74LS10

Triple 3-Input NAND Gates

文件:120.85 Kbytes Page:6 Pages

NSC

国半

DM74LS10

Triple 3-Input NAND Gate

ONSEMI

安森美半导体

Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition t

FAIRCHILD

仙童半导体

Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition t

FAIRCHILD

仙童半导体

Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition t

FAIRCHILD

仙童半导体

Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition t

FAIRCHILD

仙童半导体

Triple 3-Input NAND Gate

General Description This device contains three independent gates each of which performs the logic NAND function.

FAIRCHILD

仙童半导体

Triple 3-Input NAND Gate

General Description This device contains three independent gates each of which performs the logic NAND function.

SYC

Triple 3-Input NAND Gate

General Description This device contains three independent gates each of which performs the logic NAND function.

SYC

Triple 3-Input NAND Gate

General Description This device contains three independent gates each of which performs the logic NAND function.

FAIRCHILD

仙童半导体

Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

文件:119.69 Kbytes Page:6 Pages

NSC

国半

Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

文件:119.69 Kbytes Page:6 Pages

NSC

国半

Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

文件:119.69 Kbytes Page:6 Pages

NSC

国半

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

文件:135 Kbytes Page:6 Pages

NSC

国半

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

文件:135 Kbytes Page:6 Pages

NSC

国半

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

文件:135 Kbytes Page:6 Pages

NSC

国半

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

文件:135 Kbytes Page:6 Pages

NSC

国半

封装/外壳:16-DIP(0.300",7.62mm) 功能:设置(预设)和复位 包装:管件 描述:IC FF JK TYPE DUAL 1BIT 16DIP 集成电路(IC) 触发器

ONSEMI

安森美半导体

Triple 3-Input NAND Gates

文件:120.85 Kbytes Page:6 Pages

NSC

国半

Triple 3-Input NAND Gates

文件:120.85 Kbytes Page:6 Pages

NSC

国半

Triple 3-Input NAND Gates

文件:120.85 Kbytes Page:6 Pages

NSC

国半

Triple 3-Input NAND Gates

文件:120.85 Kbytes Page:6 Pages

NSC

国半

封装/外壳:14-DIP(0.300",7.62mm) 包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 描述:IC GATE NAND 3CH 3-INP 14DIP 集成电路(IC) 门和反相器

ONSEMI

安森美半导体

Triple 3-Input NAND Gates

文件:120.85 Kbytes Page:6 Pages

NSC

国半

TRIPLE 3-INPUT NAND GATE

TRIPLE 3-INPUT NAND GATE LOW POWER SCHOTTKY

MOTOROLA

摩托罗拉

TRIPLE 3-INPUT NAND GATE

TRIPLE 3-INPUT NAND GATE LOW POWER SCHOTTKY

MOTOROLA

摩托罗拉

替换型号 功能描述 生产厂家 企业 LOGO 操作

Dual J-K Positive-edge-triggered Flip-Flops(with Preset and Clear)

HITACHIHitachi Semiconductor

日立日立公司

Ouadruple 2-input Positive NAND Gates

HITACHIHitachi Semiconductor

日立日立公司

LOW POWER SCHOTTKY

ONSEMI

安森美半导体

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

TI

德州仪器

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

TI

德州仪器

LOW POWER SCHOTTKY

ONSEMI

安森美半导体

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP

MOTOROLA

摩托罗拉

DM74LS10产品属性

  • 类型

    描述

  • 型号

    DM74LS10

  • 功能描述

    触发器 Dl J-K Flip-Flop

  • RoHS

  • 制造商

    Texas Instruments

  • 电路数量

    2

  • 逻辑系列

    SN74

  • 逻辑类型

    D-Type Flip-Flop

  • 极性

    Inverting, Non-Inverting

  • 输入类型

    CMOS

  • 传播延迟时间

    4.4 ns

  • 高电平输出电流

    - 16 mA

  • 低电平输出电流

    16 mA

  • 电源电压-最大

    5.5 V

  • 最大工作温度

    + 85 C

  • 安装风格

    SMD/SMT

  • 封装/箱体

    X2SON-8

  • 封装

    Reel

更新时间:2026-5-14 22:59:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
onsemi(安森美)
25+
SOEIAJ16
3238
原装现货,免费供样,技术支持,原厂对接
onsemi(安森美)
25+
-
18746
样件支持,可原厂排单订货!
NSC
2016+
DIP
3000
只做原装,假一罚十,公司可开17%增值税发票!
TI
23+
NA
20000
全新原装假一赔十
FAIR
24+/25+
55
原装正品现货库存价优
NSC
26+
PLCC
9823
代理全系列销售,全新原装正品,价格优势,长期供应,量大可订
NS
2430+
DIP14
8540
只做原装正品假一赔十为客户做到零风险!!
FAIRCHIL
23+
SMD16
3600
绝对全新原装!现货!特价!请放心订购!
NSC
23+
原装原封
8888
专做原装正品,假一罚百!
FSC
25+23+
DIP14
18583
绝对原装正品全新进口深圳现货

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