型号 功能描述 生产厂家 企业 LOGO 操作
CY7C1360B

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1360B

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Infineon

英飞凌

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

封装/外壳:119-BGA 包装:管件 描述:IC SRAM 9MBIT PARALLEL 119PBGA 集成电路(IC) 存储器

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256K x 36/512K x 18 Synchronous Pipelined Burst SRAM

Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

文件:521.48 Kbytes Page:31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1360B产品属性

  • 类型

    描述

  • 型号

    CY7C1360B

  • 制造商

    Cypress Semiconductor

  • 功能描述

    CY7C1360B 9 Mb(256 K x 36) 3.3 V 166 MHz Synchronous Pipelined SRAM - TQFP-100

更新时间:2025-10-22 22:59:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
CYPRESS(赛普拉斯)
24+
LBGA165
7350
现货供应,当天可交货!免费送样,原厂技术支持!!!
CYPRESS/赛普拉斯
24+
NA/
3458
原装现货,当天可交货,原型号开票
CYPRESS
2016+
TQFP
9000
只做原装,假一罚十,公司可开17%增值税发票!
ADI
23+
DIP-16
6500
全新原装假一赔十
CYPRESS/赛普拉斯
24+
TSOP
8336
公司现货库存,支持实单
CYPRESS/赛普拉斯
25+
65248
百分百原装现货 实单必成
CYPRESS
17+
QFP
12000
只做全新进口原装,现货库存
CYPRESS/赛普拉斯
2450+
QFP
6540
只做原装正品假一赔十为客户做到零风险!!
Cypress
23+
119-PBGA(14x22)
36430
专业分销产品!原装正品!价格优势!
Cypress Semiconductor Corp
21+
256-LBGA
5280
进口原装!长期供应!绝对优势价格(诚信经营

CY7C1360B数据表相关新闻