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CY7C1360价格
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型号：CY7C1360A-150BGC 品牌：Cynergy 3 备注：这里有CY7C1360多少钱，2026年最近7天走势，今日出价，今日竞价，CY7C1360批发/采购报价，CY7C1360行情走势销售排行榜，CY7C1360报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
CY7C1360 | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 |   | |
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1360A and CY7C1362A SRAMs inte | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | |
CY7C1360产品属性
- 类型
描述
- 型号
CY7C1360
- 制造商
Rochester Electronics LLC
- 功能描述
- Bulk
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
CY |
20+ |
QFP |
3242 |
英卓尔科技,进口原装现货! |
|||
CYPRESS/赛普拉斯 |
25+ |
QFP |
32360 |
CYPRESS/赛普拉斯全新特价CY7C1360C-166AXC即刻询购立享优惠#长期有货 |
|||
CYPREE |
2023+ |
BGA |
53500 |
正品,原装现货 |
|||
CYPRESS/赛普拉斯 |
2022+ |
TQFP |
379 |
只做进口原装正品现货,开13%增值税票! |
|||
CYPRESS/赛普拉斯 |
2025+ |
TQFP100 |
750 |
原装进口价格优 请找坤融电子! |
|||
Cypress Semiconductor Corp |
24+25+ |
16500 |
全新原厂原装现货!受权代理!可送样可提供技术支持! |
||||
CYPRESS |
2025+ |
TQFP |
3925 |
全新原装、公司现货热卖 |
|||
CYPRESS(赛普拉斯) |
25+ |
LQFP-100 |
14093 |
正规渠道,大量现货,只等你来。 |
|||
CYPRESS |
23+ |
NA |
9808 |
进口代理原装优势供应全系列可订货QQ1304306553 |
|||
CYPRESS(赛普拉斯) |
24+ |
N/A |
6800 |
原装正品现货支持实单 |
CY7C1360芯片相关品牌
CY7C1360规格书下载地址
CY7C1360参数引脚图相关
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CY7C1360数据表相关新闻
CY7C1329H-133AXC
CY7C1329H-133AXC
2023-8-7CY7C1399B-12ZC 十年IC，一家专业军工级IC供货商
CY7C1399B-12ZC CY7C1399B-12ZC，ALTERA（阿尔特拉），军工级IC专业优势渠道
2020-7-16CY7C1399B-12ZC十年IC，一家专业军工级IC供货商
CY7C1399B-12ZC十年IC，一家专业军工级IC供货商
2020-7-15CY7C1370D-167AXI产品资料 CYPRESS/赛普拉斯
CY7C1370D-167AXI产品资料
2020-6-28CY7C1350G-133AXC公司原装现货/长期供应
全新原装
2019-3-30CY7C1354C-166AXI公司原装现货/长期供应
全新原装
2019-3-30
DdatasheetPDF页码索引
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