CY7C1347F-166AI芯片数据手册货源供应商报价-IC资料网

您好,欢迎来到114ic资料网！

114ic电子网登录注册

芯片资料

数据手册
丝印反查
库存查询
行业新闻
生产厂家
替换型号
晶体管

精确

位置：首页 > IC中文资料第534页 > CY7C1347

CY7C1347价格

参考价格：￥34.6361

型号：CY7C1347G-133AXC 品牌：CYPRESS 备注：这里有CY7C1347多少钱，2025年最近7天走势，今日出价，今日竞价，CY7C1347批发/采购报价，CY7C1347行情走势销售排行榜，CY7C1347报价。

型号	功能描述	生产厂家企业	LOGO
CY7C1347B	128K x 36 Synchronous-Pipelined Cache RAM Functional Description The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347B-100AC	128K x 36 Synchronous-Pipelined Cache RAM Functional Description The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347B-100AI	128K x 36 Synchronous-Pipelined Cache RAM Functional Description The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347B-100BGC	128K x 36 Synchronous-Pipelined Cache RAM Functional Description The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347B-100BGI	128K x 36 Synchronous-Pipelined Cache RAM Functional Description The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347B-133AC	128K x 36 Synchronous-Pipelined Cache RAM Functional Description The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347B-133AI	128K x 36 Synchronous-Pipelined Cache RAM Functional Description The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347B-133BGC	128K x 36 Synchronous-Pipelined Cache RAM Functional Description The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347B-133BGI	128K x 36 Synchronous-Pipelined Cache RAM Functional Description The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347B-166AC	128K x 36 Synchronous-Pipelined Cache RAM Functional Description The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347B-166BGC	128K x 36 Synchronous-Pipelined Cache RAM Functional Description The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347D	128K x 36 Synchronous-Pipelined Cache SRAM Functional Description This Cypress Synchronous Burst SRAM employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1347D SRAM integrate 131,072 x 36 SRA	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347D-166AC	128K x 36 Synchronous-Pipelined Cache SRAM Functional Description This Cypress Synchronous Burst SRAM employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1347D SRAM integrate 131,072 x 36 SRA	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347D-200AC	128K x 36 Synchronous-Pipelined Cache SRAM Functional Description This Cypress Synchronous Burst SRAM employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1347D SRAM integrate 131,072 x 36 SRA	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347D-225BGC	128K x 36 Synchronous-Pipelined Cache SRAM Functional Description This Cypress Synchronous Burst SRAM employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1347D SRAM integrate 131,072 x 36 SRA	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347D-250AC	128K x 36 Synchronous-Pipelined Cache SRAM Functional Description This Cypress Synchronous Burst SRAM employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1347D SRAM integrate 131,072 x 36 SRA	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347D-250BGC	128K x 36 Synchronous-Pipelined Cache SRAM Functional Description This Cypress Synchronous Burst SRAM employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1347D SRAM integrate 131,072 x 36 SRA	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-133AC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-133AI	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-133BGC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-133BGI	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-133BZC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-166AC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-166AI	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-166BGC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-166BGI	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-166BZC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-200AC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-200AI	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-200BGC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-200BGI	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-200BZC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-225AC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-225BGC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-250AC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347F-250BGC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-133AXC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-133AXI	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-133BGC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-133BGI	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-133BGXC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-133BGXI	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-133BZC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-133BZI	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-133BZXC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-133BZXI	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-166AXC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-166AXI	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-166BGC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-166BGI	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-166BGXC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-166BGXI	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-166BZC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-166BZI	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-166BZXC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-166BZXI	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-200AXC	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1347G-200AXI	4-Mbit (128K x 36) Pipelined Sync SRAM Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress

CY7C1347产品属性

类型
描述
型号
CY7C1347
制造商
Rochester Electronics LLC
功能描述
- Bulk
制造商
Cypress Semiconductor

CY7C1347供应商更多...

更新时间：2025-12-17 23:00:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市高捷芯城科技有限公司	CY7C1347F-200BGC	CYPRESS(赛普拉斯)	24+	BGA119	7350	现货供应,当天可交货!免费送样,原厂技术支持!!!	询价
深圳诚思涵科技有限公司	CY7C1347G-133ACX	CYPRESS/赛普拉斯	24+	TSOP-32	9987	公司现货库存,支持实单	询价
深圳市科芯源微电子有限公司	CY7C1347G-133ACX	CYPRESS/赛普拉斯	25+	QFP	88	原装正品,假一罚十!	询价
深圳市英卓尔科技有限公司	CY7C1347G-133ACX	CYPRESS	20+	QFP	500	样品可出,优势库存欢迎实单	询价
深圳市毅创腾电子科技有限公司	CY7C1347F-166AXC	CYRESS?	23+	TQFP	5700	绝对全新原装!现货!特价!请放心订购!	询价
深圳市福田区绿盛电子商行	CY7C1347G-133AXC	CYPRESS	2015+	SOP/QFP/PLCC	19889	一级代理原装现货,特价热卖!	询价
贸泽芯城（深圳）电子科技有限公司	CY7C1347F-166BGI	CYPRESS/赛普拉斯	23+		10000	原厂授权一级代理,专业海外优势订货,价格优势、品种	询价
深圳市胜彬电子有限公司	CY7C1347F-166BGCT	CYPRESS	22+	BGA	8000	原装正品支持实单	询价
深圳市恒达亿科技有限公司	CY7C1347G-133ACX	CY	25+	QFP	4500	全新原装、诚信经营、公司现货销售!	询价
深圳市欧立现代科技有限公司	CY7C1347F-166AXC	CYRESS	24+	TQFP	6980	原装现货,可开13%税票	询价

CY7C1347芯片相关品牌

CY7C1347规格书下载地址

CY7C1347参数引脚图相关

CY7C1347数据表相关新闻

CY7C1329H-133AXC
CY7C1329H-133AXC
2023-8-7
CY7C1370D-167AXI产品资料 CYPRESS/赛普拉斯
CY7C1370D-167AXI产品资料
2020-6-28
CY7C1350G-133AXC公司原装现货/长期供应
全新原装
2019-3-30
CY7C1354C-166AXI公司原装现货/长期供应
全新原装
2019-3-30
CY7C131-55JC公司原装现货/长期供应
瀚佳科技(深圳)有限公司专业为工厂一站式BOM配单服务
2019-3-29
CY7C1313BV18-167BZC公司原装现货/长期供应
瀚佳科技(深圳)有限公司专业为工厂一站式BOM配单服务
2019-3-29

DdatasheetPDF页码索引

P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
P100
P101
P102
P103
P104
P105
P106
P107

您好,欢迎来到114ic资料网！

CY7C1347价格

CY7C1347产品属性

CY7C1347供应商更多...

CY7C1347芯片相关品牌

CY7C1347规格书下载地址

CY7C1347参数引脚图相关

CY7C1347数据表相关新闻

CY7C1329H-133AXC

CY7C1370D-167AXI产品资料 CYPRESS/赛普拉斯

CY7C1350G-133AXC公司原装现货/长期供应

CY7C1354C-166AXI公司原装现货/长期供应

CY7C131-55JC公司原装现货/长期供应

CY7C1313BV18-167BZC公司原装现货/长期供应

DdatasheetPDF页码索引