型号 功能描述 生产厂家 企业 LOGO 操作
CY7C1347F

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1347F

4-Mbit (128K x 36) Pipelined Sync SRAM

Infineon

英飞凌

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description[1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchro

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

封装/外壳:100-LQFP 包装:管件 描述:IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路(IC) 存储器

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

封装/外壳:100-LQFP 包装:管件 描述:IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路(IC) 存储器

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

128K x 36 Synchronous-Pipelined Cache RAM

Functional Description The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

128K x 36 Synchronous-Pipelined Cache SRAM

Functional Description This Cypress Synchronous Burst SRAM employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1347D SRAM integrate 131,072 x 36 SRA

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128 K x 36) Pipelined Sync SRAM Asynchronous output enable

文件:808.8 Kbytes Page:24 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1347F产品属性

  • 类型

    描述

  • 型号

    CY7C1347F

  • 功能描述

    IC SRAM 4.5MBIT 100MHZ 100LQFP

  • RoHS

  • 类别

    集成电路(IC) >> 存储器

  • 系列

    -

  • 标准包装

    96

  • 系列

    - 格式 -

  • 存储器

    闪存

  • 存储器类型

    FLASH

  • 存储容量

    16M(2M x 8,1M x 16)

  • 速度

    70ns

  • 接口

    并联

  • 电源电压

    2.65 V ~ 3.6 V

  • 工作温度

    -40°C ~ 85°C

  • 封装/外壳

    48-TFSOP(0.724,18.40mm 宽)

  • 供应商设备封装

    48-TSOP

  • 包装

    托盘

更新时间:2025-10-21 9:58:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
CYPRESS/赛普拉斯
22+
QFP
3800
只做原装,价格优惠,长期供货。
CY
25+23+
QFP
13397
绝对原装正品全新进口深圳现货
CYPRESS/赛普拉斯
2022+
8
全新原装 货期两周
CYPRESS/赛普拉斯
23+
QFP
50000
全新原装正品现货,支持订货
CYPRESS/赛普拉斯
23+
QFP
25000
代理原装现货,假一赔十
CYPRESS
2024+
N/A
70000
柒号只做原装 现货价秒杀全网
CYPRESS/赛普拉斯
23+
QFP
6000
专业配单保证原装正品假一罚十
CYPRESS/赛普拉斯
25+
QFP
670
原装正品,假一罚十!
CYPRESS/赛普拉斯
24+
N/A
6618
公司现货库存,支持实单
CYPRESS/赛普拉斯
21+
QFP
10000
全新原装 公司现货 价格优

CY7C1347F数据表相关新闻