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CY7C1347G价格

参考价格:¥34.6361

型号:CY7C1347G-133AXC 品牌:CYPRESS 备注:这里有CY7C1347G多少钱,2026年最近7天走势,今日出价,今日竞价,CY7C1347G批发/采购报价,CY7C1347G行情走势销售排行榜,CY7C1347G报价。
型号 功能描述 生产厂家 企业 LOGO 操作
CY7C1347G

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1347G

4-Mbit (128 K x 36) Pipelined Sync SRAM Asynchronous output enable

文件:808.8 Kbytes Page:24 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 36) Pipelined Sync SRAM

Functional Description The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous i

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128 K x 36) Pipelined Sync SRAM Asynchronous output enable

文件:808.8 Kbytes Page:24 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128 K 횞 36) Pipelined Sync SRAM

文件:538.13 Kbytes Page:25 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128 K x 36) Pipelined Sync SRAM

文件:567.9 Kbytes Page:26 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

Memories for Embedded Systems - Synchronous SRAMs - Standard Sync -

INFINEON

英飞凌

4-Mbit (128 K 횞 36) Pipelined Sync SRAM

文件:538.13 Kbytes Page:25 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128 K x 36) Pipelined Sync SRAM

文件:567.9 Kbytes Page:26 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128 K x 36) Pipelined Sync SRAM Asynchronous output enable

文件:808.8 Kbytes Page:24 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

Memories for Embedded Systems - Synchronous SRAMs - Standard Sync -

INFINEON

英飞凌

封装/外壳:100-LQFP 包装:卷带(TR) 描述:IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路(IC) 存储器

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

Memories for Embedded Systems - Synchronous SRAMs - Standard Sync -

INFINEON

英飞凌

封装/外壳:119-BGA 包装:卷带(TR) 描述:IC SRAM 4.5MBIT PARALLEL 119PBGA 集成电路(IC) 存储器

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128 K x 36) Pipelined Sync SRAM Asynchronous output enable

文件:808.8 Kbytes Page:24 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128 K 횞 36) Pipelined Sync SRAM

文件:538.13 Kbytes Page:25 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128 K x 36) Pipelined Sync SRAM

文件:567.9 Kbytes Page:26 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128 K 횞 36) Pipelined Sync SRAM

文件:538.13 Kbytes Page:25 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128 K x 36) Pipelined Sync SRAM

文件:567.9 Kbytes Page:26 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128 K x 36) Pipelined Sync SRAM Asynchronous output enable

文件:808.8 Kbytes Page:24 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128 K x 36) Pipelined Sync SRAM Asynchronous output enable

文件:808.8 Kbytes Page:24 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1347G产品属性

  • 类型

    描述

  • 型号

    CY7C1347G

  • 功能描述

    IC SRAM 4.5MBIT 100MHZ 100LQFP

  • RoHS

  • 类别

    集成电路(IC) >> 存储器

  • 系列

    -

  • 标准包装

    1,000

  • 系列

    - 格式 -

  • 存储器

    RAM

  • 存储器类型

    移动 SDRAM

  • 存储容量

    256M(8Mx32)

  • 速度

    133MHz

  • 接口

    并联

  • 电源电压

    1.7 V ~ 1.95 V

  • 工作温度

    -40°C ~ 85°C

  • 封装/外壳

    90-VFBGA

  • 供应商设备封装

    90-VFBGA(8x13)

  • 包装

    带卷(TR)

  • 其它名称

    557-1327-2

更新时间:2026-3-18 22:58:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
CYPRESS
2016+
TQFP
6000
只做原装,假一罚十,公司可开17%增值税发票!
CY
24+
QFP
8000
只做自己库存,全新原装进口正品假一赔百,可开13%增
CYPRESS/赛普拉斯
25+
QFP100
32360
CYPRESS/赛普拉斯全新特价CY7C1347G-200AXC即刻询购立享优惠#长期有货
CYPRESS/赛普拉斯
2026+
QFP
88
原装正品,假一罚十!
Cypress
22+
100TQFP (14x20)
9000
原厂渠道,现货配单
CYPRESS
2540+
BGA
9854
只做原装正品假一赔十为客户做到零风险!!
Cypress
25+
8
公司优势库存 热卖中!!
CY
23+
NA
16
专业电子元器件供应链正迈科技特价代理特价,原装元器件供应,支持开发样品
CYPRESS
2015+
SOP/QFP/PLCC
19889
一级代理原装现货,特价热卖!
CY
25+
QFP
4500
全新原装、诚信经营、公司现货销售!

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