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CY7C131价格
参考价格：￥141.9960
型号：CY7C1311KV18-250BZC 品牌：Cynergy 3 备注：这里有CY7C131多少钱，2025年最近7天走势，今日出价，今日竞价，CY7C131批发/采购报价，CY7C131行情走势销售排行榜，CY7C131报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
CY7C131 | 1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 |   | |
CY7C131 | 1K x 8 Dual-Port Static RAM 文件：570.93 Kbytes Page：19 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | |
18-Mbit QDR짰 II SRAM Two-Word Burst Architecture Functional Description The CY7C1312KV18, CY7C1314KV18, and CY7C1910KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mb QDRTM-II SRAM 4-Word Burst Architecture Functional Description The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mb QDRTM-II SRAM 4-Word Burst Architecture Functional Description The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mb QDRTM-II SRAM 4-Word Burst Architecture Functional Description The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mb QDRTM-II SRAM 4-Word Burst Architecture Functional Description The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR-II SRAM 4-Word Burst Architecture Functional Description The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read o | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR-II SRAM 4-Word Burst Architecture Functional Description The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read o | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR-II SRAM 4-Word Burst Architecture Functional Description The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read o | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR-II SRAM 4-Word Burst Architecture Functional Description The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read o | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR II SRAM 4-Word Burst Architecture Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR II SRAM 4-Word Burst Architecture Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR II SRAM 4-Word Burst Architecture Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR II SRAM 4-Word Burst Architecture Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR II SRAM 4-Word Burst Architecture Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR II SRAM 4-Word Burst Architecture Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR II SRAM 4-Word Burst Architecture Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR II SRAM 4-Word Burst Architecture Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR II SRAM 4-Word Burst Architecture Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR짰 II SRAM Four-Word Burst Architecture Functional Description The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR짰 II SRAM Two-Word Burst Architecture Functional Description The CY7C1312KV18, CY7C1314KV18, and CY7C1910KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR짰 II SRAM Two-Word Burst Architecture Functional Description The CY7C1312KV18, CY7C1314KV18, and CY7C1910KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR짰 II SRAM Two-Word Burst Architecture Functional Description The CY7C1312KV18, CY7C1314KV18, and CY7C1910KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR짰 II SRAM Two-Word Burst Architecture Functional Description The CY7C1312KV18, CY7C1314KV18, and CY7C1910KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR짰 II SRAM Two-Word Burst Architecture Functional Description The CY7C1312KV18, CY7C1314KV18, and CY7C1910KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR짰 II SRAM Two-Word Burst Architecture Functional Description The CY7C1312KV18, CY7C1314KV18, and CY7C1910KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR짰 II SRAM Two-Word Burst Architecture Functional Description The CY7C1312KV18, CY7C1314KV18, and CY7C1910KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR짰 II SRAM Two-Word Burst Architecture Functional Description The CY7C1312KV18, CY7C1314KV18, and CY7C1910KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
Errata Document for CY7C1312V18 & CY7C1314V18 Functional Description The CY7C1310V18/CY7C1312V18/CY7C1314V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDRTM-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
Errata Document for CY7C1312V18 & CY7C1314V18 Functional Description The CY7C1310V18/CY7C1312V18/CY7C1314V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDRTM-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
Errata Document for CY7C1312V18 & CY7C1314V18 Functional Description The CY7C1310V18/CY7C1312V18/CY7C1314V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDRTM-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
1K x 8 Dual-Port Static Ram Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | |
CY7C131产品属性
- 类型
描述
- 型号
CY7C131
- 制造商
Cypress Semiconductor
- 功能描述
SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.4NS 165FBGA - Bulk
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
CYPRESS/赛普拉斯 |
24+ |
NA/ |
1000 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
|||
CYPRESS |
2016+ |
PLCC-52 |
8880 |
只做原装,假一罚十,公司可开17%增值税发票! |
|||
CYPRESS |
24+ |
PLCC52 |
8000 |
只做自己库存,全新原装进口正品假一赔百,可开13%增 |
|||
CYPRESS |
NEW |
PLCC-52 |
9526 |
代理全系列销售, 全新原装正品,价格优势,长期供应,量大可订 |
|||
CYPERSS |
24+ |
PLCC-52 |
401 |
只做原厂渠道 可追溯货源 |
|||
Cypress(赛普拉斯) |
25+ |
5000 |
只做原装 假一罚百 可开票 可售样 |
||||
CYPRESS |
15+ |
154 |
全新原装!优势库存热卖中! |
||||
CYPRESS(赛普拉斯) |
24+ |
LCC-52 |
14093 |
正规渠道,大量现货,只等你来。 |
|||
CYPRESS |
19+ |
BGA165 |
18974 |
||||
CY |
17+ |
BGA |
6200 |
100%原装正品现货 |
CY7C131规格书下载地址
CY7C131参数引脚图相关
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- CY7C132
- CY7C1315KV18-333BZC
- CY7C1315KV18-250BZXI
- CY7C1315KV18-250BZXC
- CY7C1315KV18-250BZI
- CY7C1315KV18-250BZC
- CY7C1314KV18-250BZXI
- CY7C1314KV18-250BZXC
- CY7C1314KV18-250BZI
- CY7C1314KV18-250BZC
- CY7C1313KV18-250BZXI
- CY7C1313KV18-250BZC
- CY7C1312KV18-333BZC
- CY7C1312KV18-300BZXI
- CY7C1312KV18-300BZXC
- CY7C1312KV18-300BZC
- CY7C1312KV18-250BZXI
- CY7C1312KV18-250BZXC
- CY7C1312KV18-250BZI
- CY7C1312KV18-250BZC
- CY7C1311KV18-250BZC
- CY7C1308SV25C-167BZXC
- CY7C130
- CY7C129
- CY7C1270KV18-400BZXC
- CY7C1265KV18-550BZXC
- CY7C1265KV18-450BZXC
- CY7C1263KV18-550BZXC
- CY7C1263KV18-400BZI
- CY7C12631KV18-400BZI
- CY7C1262XV18-450BZXC
- CY7C1262XV18-366BZXC
- CY7C1250KV18-400BZXC
- CY7C1250KV18-400BZI
- CY7C1250KV18-400BZC
- CY7C1248KV18-400BZC
- CY7C1245KV18-400BZXI
- CY7C1245KV18-400BZXC
- CY7C1168KV18-450BZXC
- CY7C1168KV18-400BZXC
- CY7C1165KV18-550BZC
- CY7C1165KV18-400BZC
- CY7C1150KV18-400BZXI
- CY7C109
- CY7C107
- CY7C057
- CY7C038
- CY7C037
- CY7C028
- CY7C027
- CY7C025
- CY7C024
- CY7C019
- CY7C018
- CY7C016
- CY7C009
- CY7C008
- CY7C006
- CY7BP
- CY7B995
- CY7B992
CY7C131数据表相关新闻
CY7C1329H-133AXC
CY7C1329H-133AXC
2023-8-7CY7C10612DV33-10ZSXI
原装代理
2022-9-2CY7C1061AV33-10ZXI 是由深圳市贸泽微电子有限公司重点推广的一款IC。
CY7C1061AV33-10ZXI 100%原装进口，可提供13%的增值税发票，请放心购买！
2021-1-6CY7C131-55JC公司原装现货/长期供应
瀚佳科技(深圳)有限公司 专业为工厂一站式BOM配单服务
2019-3-29CY7C1313BV18-167BZC公司原装现货/长期供应
瀚佳科技(深圳)有限公司 专业为工厂一站式BOM配单服务
2019-3-29CY7C1148KV18-400BZXC公司原装现货/长期供应
瀚佳科技(深圳)有限公司 专业为工厂一站式BOM配单服务
2019-3-29
DdatasheetPDF页码索引
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