Errata Document for CY7C1312V18 & CY7C1314V18

Functional Description The CY7C1310V18/CY7C1312V18/CY7C1314V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDRTM-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri

Errata Document for CY7C1312V18 & CY7C1314V18

Functional Description The CY7C1310V18/CY7C1312V18/CY7C1314V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDRTM-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri

Errata Document for CY7C1312V18 & CY7C1314V18

Functional Description The CY7C1310V18/CY7C1312V18/CY7C1314V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDRTM-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri