CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard outputs: 10 LS

具有复位功能的高速 CMOS 逻辑双路负边沿触发式 J-K 触发器

The ’HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.\n\n These flip-flops have independent J, K, Reset and Cl • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times\n• Complementary Outputs\n• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°C\n• Standard Outputs . . . . . 10 LSTTL Loads\n• Wide Operating Temperature Range . . . –55°C to 125°C\n• Significant Pow;

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：1.00769 Mbytes Page：18 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：57.26 Kbytes Page：8 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：266.53 Kbytes Page：13 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：452.31 Kbytes Page：15 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：422.72 Kbytes Page：15 Pages

丝印代码：CD74HCT73E；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard outputs: 10 LS

丝印代码：CD74HCT73E；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard outputs: 10 LS

丝印代码：CD74HCT73E；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：1.00769 Mbytes Page：18 Pages

丝印代码：CD74HCT73E；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：1.00769 Mbytes Page：18 Pages

丝印代码：HCT73M；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard outputs: 10 LS

丝印代码：HCT73M；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard outputs: 10 LS

丝印代码：HCT73M；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard outputs: 10 LS

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：422.72 Kbytes Page：15 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：452.31 Kbytes Page：15 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：266.53 Kbytes Page：13 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：57.26 Kbytes Page：8 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：422.72 Kbytes Page：15 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：266.53 Kbytes Page：13 Pages

封装/外壳：14-DIP（0.300"，7.62mm） 功能：复位 包装：卷带（TR） 描述：IC FF JK TYPE DUAL 1BIT 14DIP 集成电路（IC） 触发器

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF JK TYPE DUAL 1BIT 14SOIC 集成电路（IC） 触发器

丝印代码：HCT73M；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：1.00769 Mbytes Page：18 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：452.31 Kbytes Page：15 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：422.72 Kbytes Page：15 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：266.53 Kbytes Page：13 Pages

丝印代码：HCT73M；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：1.00769 Mbytes Page：18 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：266.53 Kbytes Page：13 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：422.72 Kbytes Page：15 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：422.72 Kbytes Page：15 Pages

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: