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CD74HC107价格

参考价格：￥1.3415

型号：CD74HC107E 品牌：TI 备注：这里有CD74HC107多少钱，2025年最近7天走势，今日出价，今日竞价，CD74HC107批发/采购报价，CD74HC107行情走势销售排行榜，CD74HC107报价。

型号	功能描述	生产厂家企业	LOGO
CD74HC107	Dual J-K Flip-Flop with Reset Negative-Edge Trigger Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .	TI 德州仪器	TI
CD74HC107	具有复位功能的高速 CMOS 逻辑双路负边沿触发式 J-K 触发器	TI 德州仪器	TI
CD74HC107	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：56.86 Kbytes Page：8 Pages	TI 德州仪器	TI
CD74HC107	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：451.69 Kbytes Page：15 Pages	TI 德州仪器	TI
CD74HC107	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：624.14 Kbytes Page：16 Pages	TI 德州仪器	TI
CD74HC107E	Dual J-K Flip-Flop with Reset Negative-Edge Trigger Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .	TI 德州仪器	TI
CD74HC107E.A	Dual J-K Flip-Flop with Reset Negative-Edge Trigger Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .	TI 德州仪器	TI
CD74HC107EE4	Dual J-K Flip-Flop with Reset Negative-Edge Trigger Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .	TI 德州仪器	TI
CD74HC107M	Dual J-K Flip-Flop with Reset Negative-Edge Trigger Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .	TI 德州仪器	TI
CD74HC107M96	Dual J-K Flip-Flop with Reset Negative-Edge Trigger Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .	TI 德州仪器	TI
CD74HC107M96.A	Dual J-K Flip-Flop with Reset Negative-Edge Trigger Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .	TI 德州仪器	TI
CD74HC107MT	Dual J-K Flip-Flop with Reset Negative-Edge Trigger Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .	TI 德州仪器	TI
CD74HC107E	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：624.14 Kbytes Page：16 Pages	TI 德州仪器	TI
CD74HC107E	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：451.69 Kbytes Page：15 Pages	TI 德州仪器	TI
CD74HC107E	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：266.26 Kbytes Page：11 Pages	TI 德州仪器	TI
CD74HC107E	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：56.86 Kbytes Page：8 Pages	TI 德州仪器	TI
CD74HC107EE4	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：451.69 Kbytes Page：15 Pages	TI 德州仪器	TI
CD74HC107EE4	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：624.14 Kbytes Page：16 Pages	TI 德州仪器	TI
CD74HC107EG4	封装/外壳：14-DIP（0.300"，7.62mm）功能：复位包装：卷带（TR）描述：IC FF JK TYPE DUAL 1BIT 14DIP 集成电路（IC）触发器	TI 德州仪器	TI
CD74HC107M	封装/外壳：14-SOIC（0.154"，3.90mm 宽）功能：复位包装：管件描述：IC FF JK TYPE DUAL 1BIT 14SOIC 集成电路（IC）触发器	TI 德州仪器	TI
CD74HC107M	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：266.26 Kbytes Page：11 Pages	TI 德州仪器	TI
CD74HC107M	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：624.14 Kbytes Page：16 Pages	TI 德州仪器	TI
CD74HC107M	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：56.86 Kbytes Page：8 Pages	TI 德州仪器	TI
CD74HC107M	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：451.69 Kbytes Page：15 Pages	TI 德州仪器	TI
CD74HC107M96	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：451.69 Kbytes Page：15 Pages	TI 德州仪器	TI
CD74HC107M96	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：266.26 Kbytes Page：11 Pages	TI 德州仪器	TI
CD74HC107M96	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：624.14 Kbytes Page：16 Pages	TI 德州仪器	TI
CD74HC107M96E4	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：624.14 Kbytes Page：16 Pages	TI 德州仪器	TI
CD74HC107M96E4	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：451.69 Kbytes Page：15 Pages	TI 德州仪器	TI
CD74HC107M96G4	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：624.14 Kbytes Page：16 Pages	TI 德州仪器	TI
CD74HC107M96G4	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：451.69 Kbytes Page：15 Pages	TI 德州仪器	TI
CD74HC107ME4	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：451.69 Kbytes Page：15 Pages	TI 德州仪器	TI
CD74HC107MG4	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：624.14 Kbytes Page：16 Pages	TI 德州仪器	TI
CD74HC107MG4	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：451.69 Kbytes Page：15 Pages	TI 德州仪器	TI
CD74HC107MT	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：266.26 Kbytes Page：11 Pages	TI 德州仪器	TI
CD74HC107MT	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：451.69 Kbytes Page：15 Pages	TI 德州仪器	TI
CD74HC107MT	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：624.14 Kbytes Page：16 Pages	TI 德州仪器	TI
CD74HC107MTE4	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：624.14 Kbytes Page：16 Pages	TI 德州仪器	TI
CD74HC107MTE4	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：451.69 Kbytes Page：15 Pages	TI 德州仪器	TI
CD74HC107MTG4	Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：451.69 Kbytes Page：15 Pages	TI 德州仪器	TI
74HC107	Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc	Philips 飞利浦	Philips
74HC107	Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J	NEXPERIA 安世	NEXPERIA
74HC107D	Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J	NEXPERIA 安世	NEXPERIA
74HC107D	Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc	Philips 飞利浦	Philips
74HC107DB	Dual JK flip-flop with reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc	Philips 飞利浦	Philips

CD74HC107产品属性

类型
描述
型号
CD74HC107
功能描述
触发器 Dual HS CMOS
RoHS
否
制造商
Texas Instruments
电路数量
2
逻辑系列
SN74
逻辑类型
D-Type Flip-Flop
极性
Inverting, Non-Inverting
输入类型
CMOS
传播延迟时间
4.4 ns
高电平输出电流
- 16 mA
低电平输出电流
16 mA
电源电压-最大
5.5 V
最大工作温度
+ 85 C
安装风格
SMD/SMT
封装/箱体
X2SON-8
封装
Reel

CD74HC107供应商更多...

更新时间：2025-12-25 23:01:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市高捷芯城科技有限公司	CD74HC107MG4	TI(德州仪器)	24+	SOP14	942	只做原装,提供一站式配单服务,代工代料。BOM配单	询价
深圳市得捷芯城科技有限公司	CD74HC107M	TI/德州仪器	24+	NA/	7950	原装现货,当天可交货,原型号开票	询价
深圳市科芯源微电子有限公司	CD74HC107E	TI/德州仪器	25+	DIP	996880	只做原装,欢迎来电资询	询价
深圳市华康联电子科技有限公司	CD74HC107M96	TI	23+	NA	20000		询价
深圳市煦洪科技有限公司	CD74HC107M96	TI/德州仪器	25+	原厂封装	10280	原厂授权代理,专注军工、汽车、医疗、工业、新能源！	询价
深圳市美思瑞电子科技有限公司	CD74HC107E	HAR	22+	PDIP	12245	现货,原厂原装假一罚十!	询价
深圳市力拓辉电子有限公司	CD74HC107M96	TI	22+		5000	只做原装鄙视假货15118075546	询价
贸泽芯城（深圳）电子科技有限公司	CD74HC107M	TI/德州仪器	23+	SOP-14	10000	原厂授权一级代理,专业海外优势订货,价格优势、品种	询价
深圳市宏世佳电子科技有限公司	CD74HC107M	TI	2025+	SOP-14	3785	全新原厂原装产品、公司现货销售	询价
深圳市一线半导体有限公司	CD74HC107M	TI	24+		4200		询价

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CD74HC107价格

CD74HC107产品属性

CD74HC107供应商更多...

CD74HC107芯片相关品牌

CD74HC107规格书下载地址

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DdatasheetPDF页码索引